Hi all
I used the sn65dsi85 chip on the TX1. How can I mount the chip and then configure the register on the chip via the I2C?.
Now I have modified BUS in dsi2lvds.c.
But how can I turn on dsi2lvds_bridge_enable?
if (!of_property_read_u32(np_dsi_panel,
"nvidia,dsi-lvds-bridge", &temp)) {
dsi->dsi2lvds_bridge_enable = (bool)temp;
OF_DC_LOG("dsi-lvds_bridge_enabled %d\n",
dsi->dsi2lvds_bridge_enable);
}
What files do I need to modify?
Thanks
Hi wf,
I think you need to add one line in your dts which indicates bridge is enabled.
dsi {
status = "okay";
nvidia,dsi-controller-vs = <DSI_VS_1>;
your panel {
status = "okay";
nvidia,dsi-lvds-bridge = <TEGRA_DSI_ENABLE>;
Hi Wayne
Thanks for your advice. Now I have modified BUS in dsi2lvds.c.
Made some modifications in arch\arm\boot\dts and arch\arm64\boot\dts
{
host1x {
dsi {
status = "okay";
nvidia,dsi-controller-vs = <DSI_VS_1>;
panel-a-wuxga-8-0 {
status = "okay";
nvidia,dsi-lvds-bridge= <TEGRA_DSI_ENABLE>;
compatible = "a,wuxga-8-0";
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <4>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <60>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_TX_ONLY>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <107>;
nvidia,out-height = <172>;
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
nvidia,out-parent-clk = "pll_d_out0";
nvidia,out-xres = <1200>;
nvidia,out-yres = <1920>;
};
dsi {
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54300000 0x0 0x00040000
0x0 0x54400000 0x0 0x00040000>;
status = "okay";
};
But the read sn65dsi85 chip register found no change.
Then Dtb decompile into dts found DSI diable.
dsi {
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54300000 0x0 0x40000 0x0 0x54400000 0x0 0x40000>;
status = "disable";
nvidia,dsi-controller-vs = <0x1>;
panel-a-wuxga-8-0 {
status = "disable";
nvidia,dsi-lvds-bridge = <0x1>;
compatible = "a,wuxga-8-0";
nvidia,dsi-instance = <0x0>;
nvidia,dsi-n-data-lanes = <0x4>;
nvidia,dsi-pixel-format = <0x3>;
nvidia,dsi-refresh-rate = <0x3c>;
nvidia,dsi-video-data-type = <0x0>;
nvidia,dsi-video-clock-mode = <0x1>;
nvidia,dsi-video-burst-mode = <0x0>;
nvidia,dsi-virtual-channel = <0x0>;
nvidia,dsi-panel-reset = <0x1>;
nvidia,dsi-power-saving-suspend = <0x1>;
nvidia,dsi-ulpm-not-support = <0x1>;
nvidia,dsi-dpd-pads = <0x4 0x8>;
nvidia,panel-rst-gpio = <0x6a 0xaa 0x0>;
nvidia,panel-bl-pwm-gpio = <0x6a 0xa8 0x0>;
Please remember the dts file has structure that may keep overwritten by other dts. As a result, the final dtb you use to flash may have been modified by others.
For example, in a.dts you enable the dsi and in b.dts, you include a.dts and disable dsi again. If you flash with b.dtb, dsi is still disabled.
Hi Wayne:
Thanks for your suggestion, I found the error. Now i have a mistake, can you help me?
This is the print message.Appeared "dvdd_lcd regulator get failed, dsi regulator get failed
"
[ 22.779169] dvdd_lcd regulator get failed
[ 22.779171] dsi regulator get failed
[[0;32m OK [0m] Created slice User Slice of ubuntu.
Starting User Manager for UID 1000...
[[0;32m OK [0m] Started Session c1 of user ubuntu.
Starting RealtimeKit Scheduling Policy Service...
Part of the code in the tegra210-jetson-cv-base-p2597-2180-a01.dts
host1x {
dc@54200000 {
status = "okay";
nvidia,dc-or-node = "/host1x/dsi";
};
dc@54240000 {
nvidia,dc-or-node = "/host1x/sor1";
};
dsi {
status = "okay";
panel-a-wuxga-8-0 {
status = "disabled";
};
panel-s-wqxga-10-1 {
status = "okay";
};
};
};
Part of the code in the tegra210-jetson-cv-base-p2597-2180-a00.dts
host1x {
/* tegradc.0 */
dc@54200000 {
status = "okay";
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
nvidia,emc-clk-rate = <300000000>;
nvidia,fb-bpp = <32>; /* bits per pixel */
nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
};
/* tegradc.1 */
dc@54240000 {
status = "okay";
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
nvidia,emc-clk-rate = <300000000>;
nvidia,cmu-enable = <1>;
nvidia,fb-bpp = <32>; /* bits per pixel */
nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
};
dsi {
nvidia,dsi-controller-vs = <DSI_VS_1>;
status = "okay";
panel-a-wuxga-8-0 {
status = "okay";
nvidia,dsi-dpd-pads = <DSIC_DPD_EN DSID_DPD_EN>;
nvidia,panel-rst-gpio = <&gpio TEGRA_GPIO(V, 2) 0>; /* PV2 */
nvidia,panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(V, 0) 0>; /* PV0 */
disp-default-out {
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
};
};
panel-s-wqxga-10-1 {
status = "okay";
nvidia,dsi-dpd-pads = <DSIC_DPD_EN DSID_DPD_EN>;
nvidia,panel-rst-gpio = <&gpio TEGRA_GPIO(V, 2) 0>; /* PV2 */
nvidia,panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(V, 0) 0>; /* PV0 */
nvidia,panel-en-gpio = <&gpio TEGRA_GPIO(V, 1) 0>; /* PV1 */
nvidia,dsi-te-gpio = <&gpio TEGRA_GPIO(Y, 2) 0>;
disp-default-out {
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
};
};
}
Part of the code in the panel-s-wqxga-10-1
host1x {
dsi {
status = "okay";
nvidia,dsi-controller-vs = <DSI_VS_1>;
panel-s-wqxga-10-1 {
status = "okay";
nvidia,dsi-lvds-bridge= <TEGRA_DSI_ENABLE>;
compatible = "s,wqxga-10-1";
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <4>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <61>;
nvidia,dsi-rated-refresh-rate = <60>;
nvidia,dsi-te-polarity-low = <TEGRA_DSI_ENABLE>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
nvidia,dsi-ganged-type = <TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT>;
nvidia,dsi-controller-vs = <DSI_VS_1>;;
Hi wf,
How does you connect DSI and lvds bridge? In fact, as I know, dsi-lvds-bridge does not verify on TX1 officially. I don’t guarantee if it could work.
Hi WayneWWW,
My chip sn65dsi85 is external power supply.Is it possible to ignore these print messages?
The chip sn65dsi85 has been configured via I2C.Now I only changed the above code, I found tegra no dsi clk output.What files need to be configured?
Thanks
Hi WayneWWW,
My chip sn65dsi85 is external power supply.Is it possible to ignore these print messages?
The chip sn65dsi85 has been configured via I2C.Now I only changed the above code, I found tegra no dsi clk output.What files need to be configured?
Thanks
Hi WayneWWW,
My chip sn65dsi85 is external power supply.Is it possible to ignore these print messages?
The chip sn65dsi85 has been configured via I2C.Now I only changed the above code, I found tegra no dsi clk output.What files need to be configured?
Thanks
Hi wf,
If you have external power supply. Please comment out the regulator in dsi.c or it may affect the driver function.
Hi WayneWWW,
Thank you for your patience.
I found the PCLK value in the printed message. But I do not know how to How to configure it.
[ 2.126468] tegradc tegradc.0: DT parsed successfully
[ 2.131738] tegradc tegradc.0: DSI: HS clock rate is 883000
[ 2.138779] tegradc tegradc.0: nominal-pclk:294264000 parent:294263672 div:1.0 pclk:294263672 291321360~320747760
[ 2.211795] tegra_mipi_cal 700e3000.mipical: Mipi cal timeout,val:40013980, lanes:c0000000
[ 2.218067] tegra_mipi_cal 700e3000.mipical: MIPI_CAL_CTRL 0x00 0x2a000000
[ 2.226415] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS 0x08 0x40013980
[ 2.234716] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS_2 0x0c 0x00000020
[ 2.243049] tegra_mipi_cal 700e3000.mipical: CILA_MIPI_CAL_CONFIG 0x14 0x00000000
[ 2.251344] tegra_mipi_cal 700e3000.mipical: CILB_MIPI_CAL_CONFIG 0x18 0x00000000
[ 2.259674] tegra_mipi_cal 700e3000.mipical: CILC_MIPI_CAL_CONFIG 0x1c 0x00000000
[ 2.268008] tegra_mipi_cal 700e3000.mipical: CILD_MIPI_CAL_CONFIG 0x20 0x00000000
[ 2.276314] tegra_mipi_cal 700e3000.mipical: CILE_MIPI_CAL_CONFIG 0x24 0x00000000
[ 2.284648] tegra_mipi_cal 700e3000.mipical: CILF_MIPI_CAL_CONFIG 0x28 0x00000000
[ 2.292955] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG 0x38 0x00000000
[ 2.301263] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG 0x3c 0x00000000
[ 2.309606] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG 0x40 0x00200200
[ 2.317915] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG 0x44 0x00000200
[ 2.326247] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG0 0x58 0x00000000
[ 2.334554] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG1 0x5c 0x00000300
[ 2.342887] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG2 0x60 0x00010010
[ 2.351183] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG_2 0x64 0x00000000
[ 2.359513] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG_2 0x68 0x00000000
[ 2.367847] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG_2 0x70 0x00200002
[ 2.376154] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG_2 0x74 0x00000002
[ 2.397085] dsi2lvds_config_lvds value=122
[ 2.399185] dsi ttttt
[ 2.401500] dvdd_lcd regulator get failed
[ 2.405454] dsi regulator get failed
[ 2.655852] tegradc tegradc.0: probed
[ 2.738113] tegradc tegradc.0: nominal-pclk:294377000 parent:750000000 div:2.5 pclk:300000000 291433230~320870930
[ 2.770297] Console: switching to colour frame buffer device 320x100
[ 2.815906] tegradc tegradc.0: fb registered
Is this position? nvidia,out-parent-clk = “pll_d_out0”;
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <216>;
nvidia,out-height = <135>;
nvidia,out-flags = <TEGRA_DC_OUT_ONE_SHOT_MODE TEGRA_DC_OUT_ONE_SHOT_LP_MODE>;
nvidia,out-parent-clk = "pll_d_out0";
nvidia,out-xres = <720>;
nvidia,out-yres = <576>;
};
display-timings {
720x576-32 {
clock-frequency = <27000000>;
hactive = <720>;
vactive = <576>;
hfront-porch = <12>;
hback-porch = <68>;
hsync-len = <64>;
vfront-porch = <5>;
vback-porch = <39>;
vsync-len = <5>;
nvidia,h-ref-to-sync = <1>;
nvidia,v-ref-to-sync = <1>;
};
};
Hi
It should be in panel-s-wqxga-10-1.c for your case.
Hi WayneWWW,
Now the clock is coming out.sn65dsi85 chip working properly.Test video can come out.
But when my chip chooses non-test mode, the black screen is displayed.
How can I show the desktop with dsi.
Thanks
Hi,
Sorry that I have less experience in this chip and not sure what is the difference between test/non-test mode. Could you see if any error from kernel?
HiWayneWWW,
I think the tegra output through HDMI not dsi.How can double-screen display， HDMI and DSI?
Hi wf,
Sorry I don’t get what you want. Do you mean the signal go to HDMI instead of DSI after non-test mode and cause DSI to blank?? If so, you can disable sor1 in device tree so that HDMI would not show.
Hi WayneWWW,
This is the print information. dsi: Tlpx mipi range violated. Where to configure?
[ 2.084546] tegradc tegradc.0: Display dc.54200000 registered with id=0
[ 2.090255] of_dc_parse_platform_data: DC OR node is connected to /host1x/dsi
[ 2.097506] display board info: id 0x0, fab 0x0
[ 2.102416] display board info: id 0x0, fab 0x0
[ 2.106785] of_dc_parse_platform_data: could not find vrr-settings node
[ 2.112974] of_dc_parse_platform_data: nvidia,hdmi-vrr-caps not present
[ 2.119551] of_dc_parse_platform_data: could not find cmu node for adobeRGB
[ 2.126649] tegradc tegradc.0: DT parsed successfully
[ 2.131949] tegradc tegradc.0: DSI: HS clock rate is 81000
[ 2.138877] tegradc tegradc.0: nominal-pclk:27000000 parent:27000000 div:1.0 pclk:27000000 26730000~29430000
[ 2.211957] tegra_mipi_cal 700e3000.mipical: Mipi cal timeout,val:40014980, lanes:c0000000
[ 2.218230] tegra_mipi_cal 700e3000.mipical: MIPI_CAL_CTRL 0x00 0x2a000000
[ 2.226575] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS 0x08 0x40014980
[ 2.234878] tegra_mipi_cal 700e3000.mipical: CIL_MIPI_CAL_STATUS_2 0x0c 0x00000020
[ 2.243211] tegra_mipi_cal 700e3000.mipical: CILA_MIPI_CAL_CONFIG 0x14 0x00000000
[ 2.251505] tegra_mipi_cal 700e3000.mipical: CILB_MIPI_CAL_CONFIG 0x18 0x00000000
[ 2.259836] tegra_mipi_cal 700e3000.mipical: CILC_MIPI_CAL_CONFIG 0x1c 0x00000000
[ 2.268170] tegra_mipi_cal 700e3000.mipical: CILD_MIPI_CAL_CONFIG 0x20 0x00000000
[ 2.276476] tegra_mipi_cal 700e3000.mipical: CILE_MIPI_CAL_CONFIG 0x24 0x00000000
[ 2.284810] tegra_mipi_cal 700e3000.mipical: CILF_MIPI_CAL_CONFIG 0x28 0x00000000
[ 2.293116] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG 0x38 0x00000000
[ 2.301424] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG 0x3c 0x00000000
[ 2.309768] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG 0x40 0x00200200
[ 2.318076] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG 0x44 0x00000200
[ 2.326408] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG0 0x58 0x00000000
[ 2.334716] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG1 0x5c 0x00000300
[ 2.343049] tegra_mipi_cal 700e3000.mipical: MIPI_BIAS_PAD_CFG2 0x60 0x00010010
[ 2.351345] tegra_mipi_cal 700e3000.mipical: DSIA_MIPI_CAL_CONFIG_2 0x64 0x00000000
[ 2.359675] tegra_mipi_cal 700e3000.mipical: DSIB_MIPI_CAL_CONFIG_2 0x68 0x00000000
[ 2.368009] tegra_mipi_cal 700e3000.mipical: DSIC_MIPI_CAL_CONFIG_2 0x70 0x00200002
[ 2.376316] tegra_mipi_cal 700e3000.mipical: DSID_MIPI_CAL_CONFIG_2 0x74 0x00000002
[ 2.397247] dsi2lvds_config_lvds value=122
[ 2.399346] dsi ttttt
[ 2.401660] dvdd_lcd regulator get failed
[ 2.405616] dsi regulator get failed
[ 2.655890] tegradc tegradc.0: dsi: Tlpx mipi range violated
[ 2.659556] tegradc tegradc.0: dsi: mipi range violated
[ 2.664881] tegradc tegradc.0: probed
[ 2.748751] tegradc tegradc.0: nominal-pclk:27000000 parent:81000000 div:3.0 pclk:27000000 26730000~29430000
[ 2.752079] Console: switching to colour frame buffer device 90x36
[ 2.769320] tegradc tegradc.0: fb registered
May I ask did you comment out the “dvdd_lcd regulator get failed” checking in previous comment?
Hi WayneWWW,
Do you think this error "dvdd_lcd regulator get failed"is negligible? I am using an external power supply.“Dsi: Tlpx mipi range violated” how to solve this error?
I don’t know. Because regulator failed would cause following checking in your panel drivers to skip and I don’t know if those are necessary for you.