I had tested TI TUSB7340 EVM board on TX2 pcie bus and it worked well.
Now I mount TUSB7340 chip on our custom board but there is no any devices can be detected.
root@tegra-ubuntu:/sys/bus/pci/slots# dmesg | grep pci
[ 0.142857] node /plugin-manager/fragment-500-pcie-config match with board >=3310-1000-500
[ 0.143575] node /plugin-manager/fragment-500-e3325-pcie match with board >=3310-1000-500
[ 0.264996] iommu: Adding device 10003000.pcie-controller to group 50
[ 14.697444] tegra-pcie 10003000.pcie-controller: 4x1, 1x1 configuration
[ 14.707856] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[ 14.848555] tegra-pcie 10003000.pcie-controller: probing port 0, using 4 lanes
[ 14.850769] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[ 15.273071] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 15.675071] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 16.078488] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 16.080501] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[ 16.482501] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 16.885646] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 17.290227] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 17.292246] tegra-pcie 10003000.pcie-controller: link 2 down, ignoring
[ 17.292253] tegra-pcie 10003000.pcie-controller: PCIE: no end points detected
[ 17.292433] tegra-pcie 10003000.pcie-controller: PCIE: Disable power rails
I’m not sure if it is power sequence issue.
Should I need to control PERST (PCIe reset pin) which connect to TX2 C49 (PEX0_RST) by myself?
BTW, I use default ODMDATA=0x1090000. Currently our custom board use usn3.01, usb2.02, usb-otg(for flash image), and one pcie-usb bridge(4 ports usb2.0). I think default configuration #2 of USB lane mapping is okay for us, right?
USB3.01 and USB2.02 can work well now. just PCIe doesn’t work
Is it possible that I can control TX2 C49 (PEX0_RST) that is connected to PCIe-USB bridge chip (PERST)?
Because this reset pin should be high after PCIe-USB bridge chip works.
Previously, on TX2 kit + PCie-USB bridge EMV board, this reset pin actives high automatically.
So I want to control this pin manually if it is possible can control it.
I’m not sure what you meant by “controlling PERST manually”?
We have a register that controls PERST.
BTW, don’t we have PERST routing on your board? If yes, then it is expected that end point didn’t receive any reset from root port and hence link is not coming up.
For the previous PERST question, according to PCIe-USB bridge spec, PERST should be pulled up after CLK 100us and Power on 100ms. Currently PERST and CLK trigger at the same time. Is it possible that TX2 can fit this requirement by modifying driver or registers?
You can program ‘AFI_PEX[0/1/2]_CTRL_0’ register’s PEX[0/1/2]_RST_L field to ‘0’ to pull PERST# line to low.
You can refer to pci-tegra.c file to see how is this done to apply fundamental reset to PCIe end point device
We saw “PERST” pin(C49 PEX0_RST) had a pulse when the board boot up and we don’t want it happen.
Please advise where to set “PERST” pin(C49 PEX0_RST) to low at the beginning of the driver in pci-tegra.c.
If possible, could you please start a different thread as the original issue discussed in this thread got resolved already?
Also, when you start the new thread, please do attach the output of ‘sudo lspci -vvvv’.