Tk1 FPGA-TX to CSI-A

Jinyo · October 30, 2017, 3:05pm

Hi all.

We made a custom board based on TK1.
We connect the CSI-A to the FPGA-TX.
We are feeding the CSI-A data(4-lanes) using an FPGA.

this is my architecture , please see the attach file
https://drive.google.com/drive/folders/0BxmJEALb7dhlRHItTTcxdXpfZUE

kernel version: R21.5
In order to integrate into the V4L2 (soc_camera) mechanism, we implement a Camera sensor driver for the FPGA-TX.

We modified board-ardbeg-sensor.c–> register Camera Sensor platform device.

static struct tegra_camera_platform_data ardbeg_csi_A_camera_platform_data = {
	.flip_v                 = 0,
	.flip_h                 = 0,
	.port                   = TEGRA_CAMERA_PORT_CSI_A,
	.lanes                  = 4,
	.continuous_clk         = 0,
};

static int ardbeg_csi_A_power(struct device *power, int enable){
	;
}

/* Jinyo camera sensor data */
static struct i2c_board_info ardbeg_jinyo_csi_A_camera_i2c_device = {
	I2C_BOARD_INFO("jinyo_csi", 0x1a),
};

static struct soc_camera_link ardbeg_jinyo_csi_A_soc_camera_link = {
	.bus_id         = 0, /* This must match the .id of tegra_vi01_device */
	.module_name    = "soc_camera_platform",
	.priv		= &ardbeg_csi_A_camera_platform_data,
	.i2c_adapter_id = 2,
	.board_info	= &ardbeg_jinyo_csi_A_camera_i2c_device,
	.power		= ardbeg_csi_A_power,
};

static struct platform_device ardbeg_jinyo_csi_A_soc_camera_device = {
	.name   = "soc-camera-pdrv",
	.id     = SOC_CAMERA_PLATFORM_DEVICE_LUMENS_CSI_A_ID,
	.dev    = {
		.platform_data = &ardbeg_jinyo_csi_A_soc_camera_link,
	},
};

static int ardbeg_camera_init(void)
{
		:
	platform_device_register(&ardbeg_jinyo_csi_A_soc_camera_device );
}

we use v4l2 sapmle code (capture.c v4l2 capture example · GitHub ) to capture frames.
size : 1280x720P
format : YUYV

this is our waveform ,please see the attach file

Capture Frame ,Enter HS-Mode
https://drive.google.com/drive/folders/0BxmJEALb7dhlNEliTFRISWx1dEU
HS_mode sync sequence
https://drive.google.com/drive/folders/0BxmJEALb7dhlVjVGZHJJUHRuVjA

This is Error Message:

/opt # ./v4l2Capture -c 2 -m -o -f

[   23.287307] vi vi.0: CSI_A syncpt timeout, syncpt = 4, err = -11
[   23.293308] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000010

[   23.298005] TEGRA_CSI_CSI_CILA_STATUS 0x00040041

[   23.302613] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000010

[   23.307307] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[   23.315338] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[   23.321438] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[   23.326136] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000080

[   23.331611] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[   23.337089] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000004

[   23.341872] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000

/opt # ./v4l2Capture -c 2 -m -o -f
[   27.427399] TEGRA_CSI_CSI_CILA_STATUS 0x00000001

[   27.434763] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[   27.439980] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[   27.444689] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[   27.449391] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[   27.454099] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000080

[   27.459579] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[   27.465058] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000004

[   27.469842] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[   27.674313] vi vi.0: CSI_A syncpt timeout, syncpt = 8, err = -11

[   27.680327] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[   27.686419] TEGRA_CSI_CSI_CILA_STATUS 0x00000001

[   27.693782] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[   27.699022] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[   27.703741] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[   27.708481] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[   27.713226] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000080

[   27.718747] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[   27.724266] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000004

[   27.729089] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000

[   27.933459] vi vi.0: CSI_A syncpt timeout, syncpt = 10, err = -11
[   27.939605] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[   27.944336] TEGRA_CSI_CSI_CILA_STATUS 0x00000001

[   27.948981] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[   27.953712] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[   27.958442] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[   27.963173] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[   27.967903] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000080

[   27.973410] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[   27.978922] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000004

[   27.983717] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000

Q1:
What are these errors means in CSI status register? I have checked TRM (technical reference manual), but do not understand.
Q2:
What register should I change?

thanks…

ShaneCCC · October 31, 2017, 9:43am

@Jinyo
It’s possibe cause by

CILCLK too slow
THS_SETTLE too short
THS_SETTLE too long

For the THS_SETTLE you can try to modify the TEGRA_PHY_CILx_CONTROL0 from 0x1 - 0x0F current default is hard code as 0x9
…/kernel/drivers/media/platform/soc_camera/tegra_camera/vi2.c

Jinyo · November 1, 2017, 7:17am

H1 ! ShaneCCC
Thank you for your advice …

1. THS_SETTLE too short/long
I tried it, but it doesn’t works.
TEGRA_CSI_PHY_CILA_CONTROL0 → 0x1~0xF
TEGRA_CSI_PHY_CILB_CONTROL0 → 0x1~0xF

2. CILCLK too slow

Q1:
Our MIPI clock is 148.5Mhz, this is too slow? (For 720P60)
Our format is 720P60 YUYV.

I have another question.
kernel: R21.5
file : /kernel/drivers/media/platform/soc_camera/tegra_camera/vi2.c
function : vi2_capture_setup_csi_0()

Q2: Why the YUV format is not set?

Q3: In TEGRA_VI_CSI_0_IMAGE_DEF–>BYPASS_PXL_TRANSFORM
This field is enabled. Why?

static int vi2_capture_setup_csi_0(struct tegra_camera_dev *cam,
				    struct soc_camera_device *icd)
{						:
	if ((icd->current_fmt->code == V4L2_MBUS_FMT_UYVY8_2X8) ||
		(icd->current_fmt->code == V4L2_MBUS_FMT_VYUY8_2X8) ||
		   (icd->current_fmt->code == V4L2_MBUS_FMT_YUYV8_2X8) ||
		   (icd->current_fmt->code == V4L2_MBUS_FMT_YVYU8_2X8)) {
		/* TBD */    
		
	} else if ((icd->current_fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8) ||
		   (icd->current_fmt->code == V4L2_MBUS_FMT_SGBRG8_1X8)) {
			format = TEGRA_IMAGE_FORMAT_T_L8;
			data_type = TEGRA_IMAGE_DT_RAW8;
			image_size = icd->user_width;
	} else if ((icd->current_fmt->code == V4L2_MBUS_FMT_SBGGR10_1X10) ||
		   (icd->current_fmt->code == V4L2_MBUS_FMT_SRGGB10_1X10)) {
		format = TEGRA_IMAGE_FORMAT_T_R16_I;
		data_type = TEGRA_IMAGE_DT_RAW10;
		image_size = (icd->user_width * 10) >> 3;
	}

	TC_VI_REG_WT(cam, TEGRA_VI_CSI_0_IMAGE_DEF,
			(cam->tpg_mode ? 0 : 1 << 24) | (format << 16) | 0x1);   

							:
}

I modified vi2_capture_setup_csi_0()
1. add YUYV format
2. disable BYPASS_PXL_TRANSFORM

such like:

static int vi2_capture_setup_csi_0(struct tegra_camera_dev *cam,
				    struct soc_camera_device *icd)
{						:
	if ((icd->current_fmt->code == V4L2_MBUS_FMT_UYVY8_2X8) ||
		(icd->current_fmt->code == V4L2_MBUS_FMT_VYUY8_2X8) ||
		   (icd->current_fmt->code == V4L2_MBUS_FMT_YUYV8_2X8) ||
		   (icd->current_fmt->code == V4L2_MBUS_FMT_YVYU8_2X8)) {
		   
		format = TEGRA_IMAGE_FORMAT_T_Y8_U8__Y8_V8;
		data_type = TEGRA_IMAGE_DT_YUV422_8;
		image_size = icd->user_width * 2;/*1280x2 = 2560*/
		
	} 

	TC_VI_REG_WT(cam, TEGRA_VI_CSI_0_IMAGE_DEF,(format << 16) | TEGRA_IMAGE_DEST_TO_MEM);
	TC_VI_REG_WT(cam, TEGRA_VI_CSI_0_CSI_IMAGE_DT, data_type); 
	TC_VI_REG_WT(cam, TEGRA_VI_CSI_0_CSI_IMAGE_SIZE_WC, image_size); 
	TC_VI_REG_WT(cam, TEGRA_VI_CSI_0_CSI_IMAGE_SIZE,(icd->user_height << 16) | icd->user_width);
	TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND, 0xf005);
}

Now, I can grab frame-data but still have errors

frame data is incomplete ,please see the attach file
https://drive.google.com/drive/folders/0BxmJEALb7dhlb0ptOWY5dHhvT2M
error messae

$ ./v4l2Capture -c 1 -m -o -f
[   26.788353] vi vi.0: CSI_A syncpt timeout, syncpt = 4, err = -11
[   26.794354] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000010
[   26.799050] TEGRA_CSI_CSI_CILA_STATUS 0x00040041
[   26.803659] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000010
[   26.808355] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[   26.813049] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[   26.817744] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[   26.822465] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000090
[   26.827941] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[   26.833419] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000006
[   26.838201] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
[   26.847430] mc-err: [mcerr] (vi) csw_viw: EMEM decode error on PDE or PTE entry
[   26.854726] mc-err: [mcerr]   status = 0x60010072; addr = 0x80378a00
[   26.860891] mc-err: [mcerr]   secure: no, access-type: write, SMMU fault: nr-nw-s

$ ./v4l2Capture -c 1 -m -o -f
[   38.699354] vi vi.0: CSI_A syncpt timeout, syncpt = 6, err = -11
[   38.705358] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000000
[   38.710068] TEGRA_CSI_CSI_CILA_STATUS 0x00000000
[   38.714690] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000000
[   38.719395] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[   38.724096] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[   38.728795] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[   38.733494] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000090
[   38.738973] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[   38.744450] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000006
[   38.749233] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000

Q4: TEGRA_CSI_CSI_CIL_x_STATUS Sometimes there is no error, why?
Q5: New error message:
mc-err: [mcerr] (vi) csw_viw: EMEM decode error on PDE or PTE entry
mc-err: [mcerr] status = 0x60010072; addr = 0x80378a00
mc-err: [mcerr] secure: no, access-type: write, SMMU fault: nr-nw-s
What does it mean?

thanks …

ShaneCCC · November 1, 2017, 7:45am

@Jinyo
Because the TK1 didn’t have YUV sensor reference board to verify so the code not complete.
The parser show short frame that means the sensor output size not as expect. Do you make sure the output is YUV422_8 ?

kayccc · November 9, 2017, 1:39am

Hi Jinyo,

Have all the concerns removed and continued on developing?
Any further information can be shared?

Thanks

Jinyo · November 9, 2017, 9:12am

H1 ! ShaneCCC & kayccc
Thank you for your reply …
We solved the problem of incomplete frame-data.
Now, CSI has been able to receive the frame-data transmitted by FPGA-Tx.
The frame-data size that CSI receives from FPGA-Tx is correct.

Such like:
Capture 1920x1080P YUYV422

$ hexdump frame-1.raw 
0000000 bf00 bf00 bf00 bf00 bf00 bf00 bf00 bf00
0000010 bf00 bf00 bf01 bf00 bf01 bf00 bf01 bf00
0000020 bf01 bf00 bf02 bf00 bf02 bf00 bf02 bf00
          :
03f47d0 bf6c bf0e bf6d bf0e bf6d bf0e bf6d bf0e
03f47e0 bf6d bf0e bf6e bf0e bf6e bf0e bf6e bf0e
03f47f0 bf6e bf0e bf6f bf0e bf6f bf0e bf6f bf0e
03f4800

0x3f4800 = 4147200 bytes = (1920*2)*1080 bytes

now,
We found that sometimes the CSI still shows an error message.
It does not happen often.

this is error message :

1.  [ 1206.907725] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000011
[ 1206.912421] TEGRA_CSI_CSI_CILA_STATUS 0x00050040
[ 1206.917031] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000011
[ 1206.921726] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 1206.926421] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 1206.931116] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 1206.935811] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 1206.941287] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 1206.946765] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 1206.951548] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000
or
2. [ 1196.771322] TEGRA_CSI_CSI_CIL_A_STATUS 0x00000001
[ 1196.776017] TEGRA_CSI_CSI_CILA_STATUS 0x00010000
[ 1196.780625] TEGRA_CSI_CSI_CIL_B_STATUS 0x00000001
[ 1196.785319] TEGRA_CSI_CSI_CIL_C_STATUS 0x00000000
[ 1196.790039] TEGRA_CSI_CSI_CIL_D_STATUS 0x00000000
[ 1196.794736] TEGRA_CSI_CSI_CIL_E_STATUS 0x00000000
[ 1196.799431] TEGRA_CSI_CSI_PIXEL_PARSER_A_STATUS 0x00000000
[ 1196.804906] TEGRA_CSI_CSI_PIXEL_PARSER_B_STATUS 0x00000000
[ 1196.810381] TEGRA_VI_CSI_0_ERROR_STATUS 0x00000000
[ 1196.815161] TEGRA_VI_CSI_1_ERROR_STATUS 0x00000000

Q1:
Error message:

What does it mean?

Does this mean that switching to LP01 failed?

Is TLPX time too short?

What is the range of TLPX and THS-SETTLE?

Q2:
This is our MIPI Clock (4-lanes)
720P60 = 148.5MHz
1080P60 = 297MHz

Is 148.MHz too low?
What is the lowest frequency of Tk1-CSI?

thanks …

ShaneCCC · November 17, 2017, 6:22am

It’s possible the LP01 is too short to sampling. You should probe the mipi single to make sure it’s as MIPI spec.

External Media

Jinyo · November 17, 2017, 7:08am

Hi ! ShaneCCC
Thank you for your reply …
I will confirm the LP01/TLPX interval.

What is the maximum value of TPLX?
MIPI specifications only indicate that a minimum of 50ns is required.
Is there an ideal range?

thanks …