Hi,
I’m sorry for my poor English. :(
I’m using TX2 with LT28.1
I want to capture video from HD-SDI camera. So I make a board that convert HD-SDI to MIPI with Lattice FPGA.
This board is not use I2C, just pre-configured. 1280x720p60, RGB888.
So I modifed drivers\media\i2c\ov5693.c source.
- change defined
#define OV5693_DEFAULT_MODE OV5693_MODE_1280X720_120FPS //OV5693_MODE_2592X1944 //
#define OV5693_DEFAULT_HDR_MODE OV5693_MODE_2592X1944_HDR
#define OV5693_DEFAULT_WIDTH 1280 //2592 //
#define OV5693_DEFAULT_HEIGHT 720 //1944 //
#define OV5693_DEFAULT_DATAFMT MEDIA_BUS_FMT_RGB888_1X24 //MEDIA_BUS_FMT_SBGGR12_1X12 //
#define OV5693_DEFAULT_CLK_FREQ 24000000
- ov5693_read_reg(), ov5693_write_reg(), ov5693_write_table() fuctions do nothing.
Like this.
static inline int ov5693_read_reg(struct camera_common_data *s_data, u16 addr, u8 *val)
{
return 0;
}
- In ov5693_read_otp_bank() funtion,
err = ov5693_write_reg(priv->s_data, OV5693_OTP_LOAD_CTRL_ADDR, 0x01);
if (err)
return err;
usleep_range(10000, 11000);
err = regmap_bulk_read(priv->regmap, addr, buf, size);
err = 0; // <<-- Add this line, for normal return.
if (err)
return err;
err = ov5693_write_table(priv,
mode_table[OV5693_MODE_STOP_STREAM]);
if (err)
return err;
In drivers\media\platform\tegra\camera\camera_common.c
static const struct camera_common_colorfmt camera_common_color_fmts[] = {
{
MEDIA_BUS_FMT_SRGGB12_1X12,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_SRGGB12,
},
{
MEDIA_BUS_FMT_SRGGB10_1X10,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_SRGGB10,
},
{
MEDIA_BUS_FMT_SBGGR10_1X10,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_SBGGR10,
},
{
MEDIA_BUS_FMT_SRGGB8_1X8,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_SRGGB8,
},
/*
* The below two formats are not supported by VI4,
* keep them at the last to ensure they get discarded
*/
{
MEDIA_BUS_FMT_XRGGB10P_3X10,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_XRGGB10P,
},
{
MEDIA_BUS_FMT_XBGGR10P_3X10,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_XRGGB10P,
},
{ // <<- Add this block
MEDIA_BUS_FMT_RGB888_1X24,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_RGB24,
},
};
In drivers\media\platform\tegra\camera\
static int extract_pixel_format(
const char *pixel_t, u32 *format)
{
size_t size = strnlen(pixel_t, OF_MAX_STR_LEN);
if (strncmp(pixel_t, "bayer_bggr10", size) == 0)
*format = V4L2_PIX_FMT_SBGGR10;
else if (strncmp(pixel_t, "bayer_rggb10", size) == 0)
*format = V4L2_PIX_FMT_SRGGB10;
else if (strncmp(pixel_t, "bayer_bggr12", size) == 0)
*format = V4L2_PIX_FMT_SBGGR12;
else if (strncmp(pixel_t, "bayer_rggb12", size) == 0)
*format = V4L2_PIX_FMT_SRGGB12;
else if (strncmp(pixel_t, "bayer_wdr_pwl_rggb12", size) == 0)
*format = V4L2_PIX_FMT_SRGGB12;
else if (strncmp(pixel_t, "bayer_xbggr10p", size) == 0)
*format = V4L2_PIX_FMT_XBGGR10P;
else if (strncmp(pixel_t, "bayer_xrggb10p", size) == 0)
*format = V4L2_PIX_FMT_XRGGB10P;
else if (strncmp(pixel_t, "rgb888", size) == 0) // <<-- Add this block
*format = V4L2_PIX_FMT_RGB24;
else {
pr_err("%s: Need to extend format%s\n", __func__, pixel_t);
return -EINVAL;
}
return 0;
}
And I make hardware\nvidia\platform\t18x\quill\kernel-dts\camera-dummy.dtsi file.
#include "dt-bindings/clock/tegra186-clock.h"
#define CAM0_RST_L TEGRA_MAIN_GPIO(R, 5)
#define CAM0_PWDN TEGRA_MAIN_GPIO(R, 0)
/ {
host1x {
vi@15700000 {
num-channels = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_vi_in0: endpoint {
status = "okay";
csi-port = <0>;
bus-width = <2>;
remote-endpoint = <&e3326_csi_out0>;
};
};
};
};
vi_base: vi@15700000 {
ports {
vi_port0: port@0 {
status = "okay";
vi_in0: endpoint {
status = "okay";
};
};
};
};
nvcsi@150c0000 {
num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_csi_in0: endpoint@0 {
status = "okay";
csi-port = <0>;
bus-width = <2>;
remote-endpoint = <&e3326_ov5693_out0>;
};
};
port@1 {
reg = <1>;
e3326_csi_out0: endpoint@1 {
status = "okay";
remote-endpoint = <&e3326_vi_in0>;
};
};
};
};
};
csi_base: nvcsi@150c0000 {
csi_chan0: channel@0 {
status = "okay";
ports {
csi_chan0_port0: port@0 {
status = "okay";
csi_in0: endpoint@0 {
status = "okay";
};
};
csi_chan0_port1: port@1 {
status = "okay";
csi_out0: endpoint@1 {
status = "okay";
};
};
};
};
};
};
i2c@3180000 {
ov5693_c@36 {
compatible = "nvidia,ov5693";
/* I2C device address */
reg = <0x36>;
/* V4L2 device node location */
devnode = "video0";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
/* Sensor output flip settings */
vertical-flip = "true";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
/* mclk-index indicates the index of the */
/* mclk-name with in the clock-names array */
clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
clock-frequency = <24000000>;
reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
vana-supply = <&en_vdd_cam_hv_2v8>;
vif-supply = <&en_vdd_cam>;
/**
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* mclk_khz = "";
* Standard MIPI driving clock, typically 24MHz
*
* num_lanes = "";
* Number of lane channels sensor is programmed to output
*
* tegra_sinterface = "";
* The base tegra serial interface lanes are connected to
*
* discontinuous_clk = "";
* The sensor is programmed to use a discontinuous clock on MIPI lanes
*
* dpcm_enable = "true";
* The sensor is programmed to use a DPCM modes
*
* cil_settletime = "";
* MIPI lane settle time value.
* A "0" value attempts to autocalibrate based on mclk_multiplier
*
*
*
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* line_length = "";
* Pixel line length (width) for sensor mode.
* This is used to calibrate features in our camera stack.
*
* mclk_multiplier = "";
* Multiplier to MCLK to help time hardware capture sequence
* TODO: Assign to PLL_Multiplier as well until fixed in core
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
*
*
*
* inherent_gain = "";
* Gain obtained inherently from mode (ie. pixel binning)
*
* min_gain_val = ""; (floor to 6 decimal places)
* max_gain_val = ""; (floor to 6 decimal places)
* Gain limits for mode
*
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (us)
*
*
* min_hdr_ratio = "";
* max_hdr_ratio = "";
* HDR Ratio limits for mode
*
* min_framerate = "";
* max_framerate = "";
* Framerate limits for mode (fps)
*/
mode0 { // OV5693_MODE_2592X1944
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_c";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1944";
//pixel_t = "bayer_bggr";
pixel_t = "rgb888";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode1 { //OV5693_MODE_2592X1458
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_c";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "2592";
active_h = "1458";
//pixel_t = "bayer_bggr";
pixel_t = "rgb888";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
mode2 { //OV5693_MODE_1280X720
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_c";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
//pixel_t = "bayer_bggr";
pixel_t = "rgb888";
readout_orientation = "90";
line_length = "1752";
inherent_gain = "1";
mclk_multiplier = "3.08";
pix_clk_hz = "74000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "2.787078";
max_framerate = "120";
min_exp_time = "22";
max_exp_time = "358733";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_ov5693_out0: endpoint {
csi-port = <0>;
bus-width = <2>;
remote-endpoint = <&e3326_csi_in0>;
};
};
};
};
e3326_cam0: ov5693_c@36 {
status = "okay";
};
};
tegra-camera-platform {
/**
* tpg_max_iso = <>;
* Max iso bw for 6 streams of tpg
* streams * nvcsi_freq * PG_bitrate / RG10 * BPP
* 6 * 102Mhz * 32 bits/ 10 bits * 2 Bps
* = 3916.8 MBps
*/
tpg_max_iso = <3916800>;
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <4>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <160000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. “rear” or “front”.
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module0 {
badge = "e3326_front_P5V27C";
position = "front";
orientation = "0";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ov5693 2-0036";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/ov5693_c@36";
};
};
};
};
tcp: tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
modules {
cam_module0: module0 {
status = "okay";
cam_module0_drivernode0: drivernode0 {
status = "okay";
};
};
};
};
/* set camera gpio direction to output */
gpio@2200000 {
camera-control-input {
status = "disabled";
};
camera-control-output-low {
gpio-hog;
gpios = <CAM0_RST_L 0 CAM0_PWDN 0>;
label = "cam0-rst", "cam0-pwdn";
output-low;
status = "okay";
};
camera-control-output-high {
status = "disabled";
};
};
};
Then I modified hardware\nvidia\platform\t18x\quill\kernel-dts\tegra186-quill-p3310-a00-00-base.dts
#include <t18x-common-platforms/tegra186-quill-common-p3310-1000-a00.dtsi>
#include <t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi>
//#include <t18x-common-platforms/tegra186-quill-camera-modules.dtsi> // <<-- comment out
#include <t18x-common-modules/tegra186-display-e3320-1000-a00.dtsi>
/* comms dtsi file should be included after gpio dtsi file */
#include <t18x-common-platforms/tegra186-quill-comms.dtsi>
#include <t18x-common-plugin-manager/tegra186-quill-p3310-1000-a00-plugin-manager.dtsi>
#include <t18x-common-modules/tegra186-super-module-e2614-p2597-1000-a00.dtsi>
#include <t18x-common-plugin-manager/tegra186-quill-display-plugin-manager.dtsi>
#include <t18x-common-prod/tegra186-priv-quill-p3310-1000-a00-prod.dtsi>
//#include <t18x-common-plugin-manager/tegra186-quill-camera-plugin-manager.dtsi> // <<-- comment out
#include <camera-dummy.dtsi> // <<-- Add this line
#include <dt-bindings/linux/driver-info.h>
Then, compile & download.
when run below command
v4l2-ctl --device /dev/video0 --stream-mmap --stream-to=frame0.raw --stream-count=1 --verbose
dmesg is
[ 7554.447351] tegra_mipi_cal 3990000.mipical: Mipi cal timeout,val:8861, lanes:100000
[ 7554.455084] tegra_mipi_cal 3990000.mipical: MIPI_CAL_CTRL 0x04 0x2a000010
[ 7554.463435] tegra_mipi_cal 3990000.mipical: CIL_MIPI_CAL_STATUS 0x0c 0x00008861
[ 7554.471864] tegra_mipi_cal 3990000.mipical: CIL_MIPI_CAL_STATUS_2 0x10 0x00000000
[ 7554.480239] tegra_mipi_cal 3990000.mipical: CILA_MIPI_CAL_CONFIG 0x18 0x00200000
[ 7554.488602] tegra_mipi_cal 3990000.mipical: CILB_MIPI_CAL_CONFIG 0x1c 0x00000000
[ 7554.496912] tegra_mipi_cal 3990000.mipical: CILC_MIPI_CAL_CONFIG 0x20 0x00000000
[ 7554.505256] tegra_mipi_cal 3990000.mipical: CILD_MIPI_CAL_CONFIG 0x24 0x00000000
[ 7554.513572] tegra_mipi_cal 3990000.mipical: CILE_MIPI_CAL_CONFIG 0x28 0x00000000
[ 7554.521899] tegra_mipi_cal 3990000.mipical: CILF_MIPI_CAL_CONFIG 0x2c 0x00000000
[ 7554.530211] tegra_mipi_cal 3990000.mipical: DSIA_MIPI_CAL_CONFIG 0x3c 0x00000200
[ 7554.538517] tegra_mipi_cal 3990000.mipical: DSIB_MIPI_CAL_CONFIG 0x40 0x00000200
[ 7554.546834] tegra_mipi_cal 3990000.mipical: DSIC_MIPI_CAL_CONFIG 0x44 0x00000200
[ 7554.555133] tegra_mipi_cal 3990000.mipical: DSID_MIPI_CAL_CONFIG 0x48 0x00000200
[ 7554.563459] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG0 0x5c 0x00000000
[ 7554.571768] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG1 0x60 0x00000000
[ 7554.580071] tegra_mipi_cal 3990000.mipical: MIPI_BIAS_PAD_CFG2 0x64 0x00010010
[ 7554.588367] tegra_mipi_cal 3990000.mipical: DSIA_MIPI_CAL_CONFIG_2 0x68 0x00000002
[ 7554.596660] tegra_mipi_cal 3990000.mipical: DSIB_MIPI_CAL_CONFIG_2 0x6c 0x00000002
[ 7554.604939] tegra_mipi_cal 3990000.mipical: DSIC_MIPI_CAL_CONFIG_2 0x74 0x00000002
[ 7554.613223] tegra_mipi_cal 3990000.mipical: DSID_MIPI_CAL_CONFIG_2 0x78 0x00000002
[ 7555.619391] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 7556.623394] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 7557.627393] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 7558.631405] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 7559.635373] tegra-vi4 15700000.vi: ATOMP_FE syncpt timeout!
Now, what should I do?
I’ve no idea.