CSI_A CSI_B Data lanes

Hi support,

We are using a board based on the Tegra K1 SOC (With kernel R21.5).

An HDMI to CSI2 bridge is connected to this board.

We configure the HDMI to CSI2 bridge to send HDMI data on 4 data lanes + 1 clk lane, using those pins

  • CSI_A_CLK_N
  • CSI_A_CLK_P
  • CSI_A_D0_N
  • CSI_A_D0_P
  • CSI_A_D1_N
  • CSI_A_D1_P
    plus
  • CSI_B_D0_N
  • CSI_B_D0_P
  • CSI_B_D1_N
  • CSI_B_D1_P

As CSI_A and CSI_B has 2 lanes each one,

How can we retrieve data received on the lanes of CSI_A and CSI_B , using a single vi V4L2 input device ?

Best regards

You can reference to the …/kernel/driver/media/i2c/soc_camera/imx135 for 4 lane sensor driver.

Thanks,

Could you confirm those lines are mandatory to enable 4 lane over CSI_A (2 data lanes + clk)+ CSI_B (2 data lanes):

static struct tegra_io_dpd csia_io = {
        .name                   = "CSIA",
        .io_dpd_reg_index       = 0,
        .io_dpd_bit             = 0,
};

static struct tegra_io_dpd csib_io = {
        .name                   = "CSIB",
        .io_dpd_reg_index       = 0,
        .io_dpd_bit             = 1,
};

@camera power on:

tegra_io_dpd_disable(&csia_io);
tegra_io_dpd_disable(&csib_io);

@camera power off:

tegra_io_dpd_enable(&csia_io);
tegra_io_dpd_enable(&csib_io);

in the DTB :

static struct tegra_camera_platform_data apalis_tk1_imx135_camera_platform_data = {
        .flip_v                 = 0,
        .flip_h                 = 0,
        .port                   = TEGRA_CAMERA_PORT_CSI_A,
        .lanes                  = 4,
        .continuous_clk         = 0,
};

We to be confidant that this will be working, please confirm this should be enough.

That’s correct.

Hello,
It worked,
Thank you.