We are presently integrating the Jetson TX2 module with a custom carrier board.
The TX2 module provides camera input clocks CAM0_MCLK and CAM1_MCLK. These are identified as “extperiph1” and “extperiph2” in the DTS. Looking at the signals with an oscilloscope, the clocks are active during video capture and idle otherwise.
We would like to keep the camera input clocks enabled at all times. Can this be configured through the tegra camera platform API? Or is there an additional clock control available through the DTS?
@ShaneCCC, could you provide a guidance or direct me to a source of documents regarding how to control the MCLKs on the CSI port in the driver? I’m running into a similar issue in designing and testing a customized device on the CSI connector.
Thanks ShaneCCC for the info.
We followed the instruction to exam our setup, and realized that our hardware is relying on MCLK to be a free running clock in order to get the i2c interface to work.
Now, to use sysfs to enable MCLK, can you provide the exact command to use?
The files under extperiph1 are:
root@tegra-ubuntu:/sys/kernel/debug/bpmp/debug/clk# ll extperiph1/
total 0
drwxr-xr-x 2 root root 0 Jan 1 2000 ./
drwxr-xr-x 385 root root 0 Jan 1 2000 ../
-r-------- 1 root root 0 Jan 1 2000 dvfs
-r-------- 1 root root 0 Jan 1 2000 max_rate
-r-------- 1 root root 0 Jan 1 2000 min_rate
-rw------- 1 root root 0 Jan 1 2000 mrq_rate_locked
-rw------- 1 root root 0 Jan 1 2000 parent
-r-------- 1 root root 0 Jan 1 2000 possible_parents
-r-------- 1 root root 0 Jan 1 2000 pto_counter
-rw------- 1 root root 0 Jan 1 2000 rate
-rw------- 1 root root 0 Jan 1 2000 state