There tried to disable PCIe SSC which only disable Kernel codes seems no influence.
Follow Spec 5.2.17 flag PLLE_SSCBYP found out uboot source code.
To mask clock.c “PLLE_SS_CNTL_SSCINC” relation codes that SSC seems be disabled (follow Source code changed:to show change points).
But can’t be sured those way are correct and will no make any side event .
Hope the nVidia TX1 experts suggest us which best way for disable PCIe SSC.
#if 0 // mask PLLE_SSCBYP flag to disable PCIe Spread Spectrum Clock(SSC)
value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
value &= ~PLLE_SS_CNTL_SSCINC(0xff);
value |= PLLE_SS_CNTL_SSCINC(1);
value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
value |= PLLE_SS_CNTL_SSCINCINTR(0x23);
value &= ~PLLE_SS_CNTL_SSCMAX(0x1fff);
value |= PLLE_SS_CNTL_SSCMAX(0x21);
value &= ~PLLE_SS_CNTL_SSCINVERT;
value &= ~PLLE_SS_CNTL_SSCCENTER;
value &= ~PLLE_SS_CNTL_BYPASS_SS;
value &= ~PLLE_SS_CNTL_SSCBYP;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
/* 6. Wait 300 ns */
udelay(1);
value &= ~PLLE_SS_CNTL_INTERP_RESET;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
Thank for your reply:
Our source code base were used JetPack-L4T-2.3.1-linux-x64.run to install development environment.
Those L4T BSP information was R28.1. I am check can’t find code static int clk_plle_tegra210_enable(struct clk_hw *hw) on our code.
Could you teach us how to disable SSC on R28.1 .