Hi,
We are developing a driver for TC358748XBG which converts Parallel to MIPI, the input will be a PAL camera (interlace), does the Jetson TX2 supports capturing interlace on MIPI? Is there a deinterlacer on the Jetson HW?
Thanks,
-David
hello DavidSoto,
would like to confirm your whole pipeline,
am I understand your use-case correctly as below?
hw->[interlace content]–>MIPI CSI—processing—>MIPI DSI–>[interlace content]->display
Hi Jerry,
Your understanding is correct:
PAL/BT656 Camera (interlace)–>TC358748XBG–>Jetson/MIPI–>[deinterlace]—>display and encode.
My questions are:
a) Can the Jetson TX2 capture interlace video?
b) Can the Jetson TX2 deinterlace video by hardware (not sw)?
c) Can the Jetson TX2 display interlace video if needed?
d) In case of needed, can the Jetson encode interlace video?
Thanks
-David
DavidSoto,
Sorry for late reply. All L4T devices don’t support interlace video on display.
Hi Wayne,
Thanks for your response, understood, not supported on the display side. What about the capture side? Basically points a), b), d) mentioned above.
-David
DavidSoto,
Only option a is being supported.
Thanks Wayne.
Hi,
I captured interlace video from MIPI CSI, but encountered some problems.
kernel log:
[ 2687.739202] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 2687.745924] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 2687.758358] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_INTR_STATUS 0x00000080
[ 2687.766448] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_ERR_INTR_STATUS 0x00000080
[ 2688.787247] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 2688.793959] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 2688.805975] nvcsi 150c0000.nvcsi: csi4_stream_check_status (3) INTR_STATUS 0x00000008
[ 2688.814101] nvcsi 150c0000.nvcsi: csi4_stream_check_status (3) ERR_INTR_STATUS 0x00000008
[ 2688.822397] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_INTR_STATUS 0x00000084
[ 2688.830374] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_ERR_INTR_STATUS 0x00000084
[ 2689.851263] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 2689.858060] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 2689.870375] nvcsi 150c0000.nvcsi: csi4_stream_check_status (3) INTR_STATUS 0x00000008
[ 2689.878462] nvcsi 150c0000.nvcsi: csi4_stream_check_status (3) ERR_INTR_STATUS 0x00000008
[ 2689.886776] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_INTR_STATUS 0x00000084
[ 2689.894773] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_ERR_INTR_STATUS 0x00000084
[ 2690.911375] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 2690.918190] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 2690.931356] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_INTR_STATUS 0x00000084
[ 2690.939437] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_ERR_INTR_STATUS 0x00000084
[ 2691.971258] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 2691.977971] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 2691.990474] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_INTR_STATUS 0x00000084
[ 2691.998581] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_ERR_INTR_STATUS 0x00000084
[ 2693.011308] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 2693.018062] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 2693.030373] nvcsi 150c0000.nvcsi: csi4_stream_check_status (3) INTR_STATUS 0x00000008
[ 2693.038475] nvcsi 150c0000.nvcsi: csi4_stream_check_status (3) ERR_INTR_STATUS 0x00000008
[ 2693.046870] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_INTR_STATUS 0x00000084
[ 2693.054895] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_ERR_INTR_STATUS 0x00000084
[ 2693.091517] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_INTR_STATUS 0x00000084
[ 2693.099898] nvcsi 150c0000.nvcsi: csi4_cil_check_status (3) CIL_ERR_INTR_STATUS 0x00000084
The `syncpt timeout’ error log only occur when capturing even fields, odd fileds are captured normally, and I can only capture 2 fields per second.
The odd fields data I captured are all right, but even fileds are all zero, which is a green image.