How to modify continuous clock of spi to non-continuous clock on tx2?

2284810331 · July 9, 2018, 6:24am

Hello,
spi clock is continus on TX2(r28.1) such as the first picture.
The second picture describe the non-continuous clock on tx1.

Thank you very much!

673790921 · July 9, 2018, 6:47am

I also had this problem,but I don’t know how to solve it…

ShaneCCC · July 12, 2018, 8:47am

Looking at the pictures, I believe he is asking for delay between packets. This is possible and has been documented. But the chip select pin used should be put in gpio mode and gpio number has to be passed.

Details in Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt

nvidia,clk-delay-between-packets : Clock delay between packets by keeping
CS active. For this, it is required to pass the Chip select
as GPIO.

nikola.latinovic · February 28, 2019, 11:14am

Hello ShaneCCC,

Can You please post some more detailed explanation about this workaround. I have to modify to non-continuous clock on TX2 spidev0.0 . I have tried (according to documentation - part of my device tree source) :

spi@3210000 {
	reg = <0x0 0x3210000 0x0 0x10000>;
	dmas = <0x19 0xf 0x19 0xf>;
	interrupts = <0x0 0x24 0x4>;
	compatible = "nvidia,tegra186-spi";
	clock-names = "spi", "pll_p", "clk_m";
	reset-names = "spi";
	clocks = <0xd 0x31 0xd 0x10d 0xd 0x261>;
	nvidia,dma-request-selector = <0x19 0xf>;
	resets = <0xd 0x28>;
	status = "okay";
	
            cs-gpios = <&tegra_main_gpio TEGRA_MAIN_GPIO(H,3) 0>; -- this line produces syntax error
            cs-gpios = <&gpio1 0 0>;                              -- this line produces syntax error
            
	#address-cells = <0x1>;
	phandle = <0x7e>;
	nvidia,clk-parents = "pll_p", "clk_m";
	#stream-id-cells = <0x1>;
	#size-cells = <0x0>;
	dma-names = "rx", "tx";
	linux,phandle = <0x7e>;

	spi@0 {
		reg = <0x0>;
		nvidia,tx-clk-tap-delau = <0x0>;
		compatible = "spidev";
		nvidia,cs-setup-clk-count = <0x1e>;
		nvidia,cs-hold-clk-count = <0x1e>;
		spi-max-frequency = <0x1312d00>;
		nvidia,enable-hw-based-cs;
		nvidia,rx-clk-tap-delay = <0x1f>;
		nvidia,clk-delay-between-packets = <0x1e>;
	};

	spi@1 {
		reg = <0x1>;
		nvidia,tx-clk-tap-delau = <0x0>;
		compatible = "spidev";
		nvidia,cs-setup-clk-count = <0x1e>;
		nvidia,cs-hold-clk-count = <0x1e>;
		spi-max-frequency = <0x1312d00>;
		nvidia,enable-hw-based-cs;
		nvidia,rx-clk-tap-delay = <0x1f>;
	};
};

Can You maybe post some example how to pass CS pin as gpio, or some example of good device tree source for spi for this problem ?

Thanks in advance,
Best regards!