please download the [L4T Documentation], you could refer to [NVIDIA Tegra Linux Driver Package]-> [Development Guide]-> [Camera Development] for [Sensor Driver Programming Guide]
By the way , I have find something wrong with kernel Oops before I get /dev/video0.
Here is the information . it tell me that something wrong with tegra_channel_fmts_bitmap_init function . And I have add
Hi askariz0503,
How you solved this problem with tegra-vi4 15700000.vi: all channel register failed and got the dev/video file?
Now I had a same problem with porting AR0135 drive to TX2.Could you help me solve this problem? Thanks a lot!
Hi all,
I am glad to say that I have successful capture the image from tc358743 driver with R28.2.1. with latance of ~100ms . Later I will provide the source code and hardware shematic to github .
Thanks all
Hi askariz0503,
Thank you very much for reply!
What is function with dtc compile? check device tree file error?
And which way you use to regist your device? Plugin maneger or Main Platform Device Tree File? I used Main Platform Device Tree File! And I used tegra186-quill-camera-modules.dtsi as a model for generating my dtsi.Here is my hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-modules/tegra186-camera-e3326-a00.dtsi:
/*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//#include "dt-bindings/clock/tegra186-clock.h" //zhou
//#include <t18x-common-platforms/tegra186-quill-camera-e3326-a00.dtsi>
/ {
host1x {
vi@15700000 {
status = "okay";
num-channels = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
status = "okay";
reg = <0>;
e3326_vi_in0: endpoint {
status = "okay";
csi-port = <2>;
bus-width = <2>;
remote-endpoint = <&e3326_csi_out0>;
};
};
};
};
nvcsi@150c0000 {
status = "okay";
num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
status = "okay";
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
status = "okay";
reg = <0>;
e3326_csi_in0: endpoint@0 {
status = "okay";
csi-port = <2>;
bus-width = <2>;
remote-endpoint = <&e3326_ar0135_out0>;
};
};
port@1 {
status = "okay";
reg = <1>;
e3326_csi_out0: endpoint@1 {
status = "okay";
remote-endpoint = <&e3326_vi_in0>;
};
};
};
};
};
};
i2c@3180000 {
status = "okay";
ar0135_c@10 {
compatible = "nvidia,ar0135";
/* I2C device address */
reg = <0x10>;
/* V4L2 device node location */
devnode = "video0";
status = "okay";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
sensor_model = "ar0135";
// clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
// <&tegra_car TEGRA186_CLK_PLLP_OUT0>;
// clock-names = "extperiph1", "pllp_grtba";
// mclk = "extperiph1";
// //clock-frequency = <24000000>;
// clock-frequency = <25000000>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
/* Sensor output flip settings */
/*vertical-flip = "true";*/
/**
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* mclk_khz = "";
* Standard MIPI driving clock, typically 24MHz
*
* num_lanes = "";
* Number of lane channels sensor is programmed to output
*
* tegra_sinterface = "";
* The base tegra serial interface lanes are connected to
*
* discontinuous_clk = "";
* The sensor is programmed to use a discontinuous clock on MIPI lanes
*
* dpcm_enable = "true";
* The sensor is programmed to use a DPCM modes
*
* cil_settletime = "";
* MIPI lane settle time value.
* A "0" value attempts to autocalibrate based on mclk_multiplier
*
*
*
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* line_length = "";
* Pixel line length (width) for sensor mode.
* This is used to calibrate features in our camera stack.
*
* mclk_multiplier = "";
* Multiplier to MCLK to help time hardware capture sequence
* TODO: Assign to PLL_Multiplier as well until fixed in core
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
*
*
*
* inherent_gain = "";
* Gain obtained inherently from mode (ie. pixel binning)
*
* min_gain_val = ""; (floor to 6 decimal places)
* max_gain_val = ""; (floor to 6 decimal places)
* Gain limits for mode
*
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (us)
*
*
* min_hdr_ratio = "";
* max_hdr_ratio = "";
* HDR Ratio limits for mode
*
* min_framerate = "";
* max_framerate = "";
* Framerate limits for mode (fps)
*/
mode0 { // AR0135_MODE_1280X728
mclk_khz = "25000";
num_lanes = "2";
tegra_sinterface = "serial_c";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "728";
pixel_t = "raw12";
readout_orientation = "90";
line_length = "1650";
inherent_gain = "1";
// mclk_multiplier = "6.67";
// pix_clk_hz = "160000000";
mclk_multiplier = "2.97";
pix_clk_hz = "74250000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "54";
min_exp_time = "34";
max_exp_time = "550385";
embedded_metadata_height = "2";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
status = "okay";
reg = <0>;
e3326_ar0135_out0: endpoint {
status = "okay";
csi-port = <2>;
bus-width = <2>;
remote-endpoint = <&e3326_csi_in0>;
};
};
};
};
};
e3326_lens_ar0135@P5V27C {
min_focus_distance = "0.0";
hyper_focal = "0.0";
focal_length = "2.67";
f_number = "2.0";
aperture = "2.0";
};
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <4>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
//max_pixel_rate = <160000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. “rear” or “front”.
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module0 {
status = "okay";
badge = "e3326_front_P5V27C";
position = "rear";
orientation = "1";
drivernode0 {
status = "okay";
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ar0135 2-0010";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/ar0135_c@10";
};
drivernode1 {
status = "okay";
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e3326_lens_ar0135@P5V27C/";
};
};
};
};
};
And hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-camera-modules.dtsi.
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
//#include "t18x-common-platforms/tegra186-quill-deserializer.dtsi"
#include "t18x-common-platforms/tegra186-quill-camera-e3326-a00.dtsi"
#include "t18x-common-platforms/tegra186-quill-camera-e3323-a00.dtsi"
#include "t18x-common-platforms/tegra186-quill-camera-e3333-a00.dtsi"
#include "t18x-common-platforms/tegra186-quill-camera-e3322-a00.dtsi"
#include "t18x-common-platforms/tegra186-quill-camera-li-mipi-adpt-a00.dtsi"
#include "t18x-common-platforms/tegra186-quill-camera-imx274-a00.dtsi"
#include "t18x-common-platforms/tegra186-quill-camera-vivid.dtsi"
#define CAM0_RST_L TEGRA_MAIN_GPIO(R, 5)
#define CAM0_PWDN TEGRA_MAIN_GPIO(R, 0)
#define CAM1_RST_L TEGRA_MAIN_GPIO(R, 1)
#define CAM1_PWDN TEGRA_MAIN_GPIO(L, 6)
/ {
tegra-camera-platform {
/**
* tpg_max_iso = <>;
* Max iso bw for 6 streams of tpg
* streams * nvcsi_freq * PG_bitrate / RG10 * BPP
* 6 * 102Mhz * 32 bits/ 10 bits * 2 Bps
* = 3916.8 MBps
*/
tpg_max_iso = <3916800>;
};
/* set camera gpio direction to output */
gpio@2200000 {
camera-control-output-low {
gpio-hog;
output-low;
gpios = <CAM0_RST_L 0 CAM0_PWDN 0
CAM1_RST_L 0 CAM1_PWDN 0>;
label = "cam0-rst", "cam0-pwdn",
"cam1-rst", "cam1-pwdn";
};
};
/* all cameras are disabled by default */
host1x {
vi_base: vi@15700000 {
status = "okay";
ports {
vi_port0: port@0 {
status = "okay";
vi_in0: endpoint {
status = "okay";
};
};
vi_port1: port@1 {
status = "disabled";
vi_in1: endpoint {
status = "disabled";
};
};
vi_port2: port@2 {
status = "disabled";
vi_in2: endpoint {
status = "disabled";
};
};
vi_port3: port@3 {
status = "disabled";
vi_in3: endpoint {
status = "disabled";
};
};
vi_port4: port@4 {
status = "disabled";
vi_in4: endpoint {
status = "disabled";
};
};
vi_port5: port@5 {
status = "disabled";
vi_in5: endpoint {
status = "disabled";
};
};
};
};
csi_base: nvcsi@150c0000 {
status = "okay";
csi_chan0: channel@0 {
status = "okay";
ports {
csi_chan0_port0: port@0 {
status = "okay";
csi_in0: endpoint@0 {
status = "okay";
};
};
csi_chan0_port1: port@1 {
status = "okay";
csi_out0: endpoint@1 {
status = "okay";
};
};
};
};
csi_chan1: channel@1 {
status = "disabled";
ports {
csi_chan1_port0: port@0 {
status = "disabled";
csi_in1: endpoint@2 {
status = "disabled";
};
};
csi_chan1_port1: port@1 {
status = "disabled";
csi_out1: endpoint@3 {
status = "disabled";
};
};
};
};
csi_chan2: channel@2 {
status = "disabled";
ports {
csi_chan2_port0: port@0 {
status = "disabled";
csi_in2: endpoint@4 {
status = "disabled";
};
};
csi_chan2_port1: port@1 {
status = "disabled";
csi_out2: endpoint@5 {
status = "disabled";
};
};
};
};
csi_chan3: channel@3 {
status = "disabled";
ports {
csi_chan3_port0: port@0 {
status = "disabled";
csi_in3: endpoint@6 {
status = "disabled";
};
};
csi_chan3_port1: port@1 {
status = "disabled";
csi_out3: endpoint@7 {
status = "disabled";
};
};
};
};
csi_chan4: channel@4 {
status = "disabled";
ports {
csi_chan4_port0: port@0 {
status = "disabled";
csi_in4: endpoint@8 {
status = "disabled";
};
};
csi_chan4_port1: port@1 {
status = "disabled";
csi_out4: endpoint@9 {
status = "disabled";
};
};
};
};
csi_chan5: channel@5 {
status = "disabled";
ports {
csi_chan5_port0: port@0 {
status = "disabled";
csi_in5: endpoint@10 {
status = "disabled";
};
};
csi_chan5_port1: port@1 {
status = "disabled";
csi_out5: endpoint@11 {
status = "disabled";
};
};
};
};
};
};
i2c@3180000 {
e3326_cam0: ar0135_c@10 {
status = "okay";
};
e3323_cam0: ov23850_a@10 {
status = "disabled";
};
e3323_vcm0: lc898212@72 {
status = "disabled";
};
tca6408@21 {
status = "disabled";
};
tca9548@77 {
status = "disabled";
i2c@0 {
e3333_cam0: ov5693_a@36 {
status = "disabled";
};
e3322_cam0: imx219_a@10 {
status = "disabled";
};
};
i2c@1 {
e3333_cam1: ov5693_b@36 {
status = "disabled";
};
e3322_cam1: imx219_b@10 {
status = "disabled";
};
};
i2c@2 {
e3333_cam2: ar0135_c@10 {
status = "disabled";
};
e3322_cam2: imx219_c@10 {
status = "disabled";
};
};
i2c@3 {
e3333_cam3: ov5693_d@36 {
status = "disabled";
};
e3322_cam3: imx219_d@10 {
status = "disabled";
};
};
i2c@4 {
e3333_cam4: ov5693_e@36 {
status = "disabled";
};
e3322_cam4: imx219_e@10 {
status = "disabled";
};
};
i2c@5 {
e3333_cam5: ov5693_f@36 {
status = "disabled";
};
e3322_cam5: imx219_f@10 {
status = "disabled";
};
};
};
tca9546_70: tca9546@70 {
status = "disabled";
i2c@0 {
imx185_cam0: imx185_a@1a {
status = "disabled";
};
};
};
tca9546_70: tca9546@70 {
status = "disabled";
i2c@0 {
imx274_cam0: imx274_a@1a {
status = "disabled";
};
};
};
};
i2c@c240000 {
e3323_cam1: ov23850_c@36 {
status = "disabled";
};
e3323_vcm1: lc898212@72 {
status = "disabled";
};
};
tcp: tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
modules {
cam_module0: module0 {
status = "okay";
cam_module0_drivernode0: drivernode0 {
status = "okay";
};
cam_module0_drivernode1: drivernode1 {
status = "okay";
pcl_id = "v4l2_lens";
};
};
cam_module1: module1 {
status = "disabled";
cam_module1_drivernode0: drivernode0 {
status = "disabled";
};
cam_module1_drivernode1: drivernode1 {
status = "disabled";
pcl_id = "v4l2_lens";
};
};
cam_module2: module2 {
status = "disabled";
cam_module2_drivernode0: drivernode0 {
status = "disabled";
};
cam_module2_drivernode1: drivernode1 {
status = "disabled";
pcl_id = "v4l2_lens";
};
};
cam_module3: module3 {
status = "disabled";
cam_module3_drivernode0: drivernode0 {
status = "disabled";
};
cam_module3_drivernode1: drivernode1 {
status = "disabled";
pcl_id = "v4l2_lens";
};
};
cam_module4: module4 {
status = "disabled";
cam_module4_drivernode0: drivernode0 {
status = "disabled";
};
cam_module4_drivernode1: drivernode1 {
status = "disabled";
pcl_id = "v4l2_lens";
};
};
cam_module5: module5 {
status = "disabled";
cam_module5_drivernode0: drivernode0 {
status = "disabled";
};
cam_module5_drivernode1: drivernode1 {
status = "disabled";
pcl_id = "v4l2_lens";
};
};
};
};
};
my hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-camera-e3326-a00.dtsi.
/*
* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <t18x-common-modules/tegra186-camera-e3326-a00.dtsi>
#include "dt-bindings/clock/tegra186-clock.h"
// #define CAM0_RST_L TEGRA_MAIN_GPIO(R, 5)
// #define CAM0_PWDN TEGRA_MAIN_GPIO(R, 0)
/* camera control gpio definitions */
/ {
i2c@3180000 {
ar0135_c@10 {
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
/* mclk-index indicates the index of the */
/* mclk-name with in the clock-names array */
clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
//clock-frequency = <24000000>;
clock-frequency = <25000000>;
// reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
// pwdn-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
vana-supply = <&en_vdd_cam_hv_2v8>;
vif-supply = <&en_vdd_cam>;
};
};
// gpio@2200000 {
// camera-control-output-low {
// gpio-hog;
// output-low;
// gpios = <CAM0_RST_L 0 CAM0_PWDN 0>;
// label = "cam0-rst", "cam0-pwdn";
// };
// };
};
glad to know you’re able to successful capture the image from tc358743 driver with R28.2.1.
may I know how you fix the PXL_SOF failure in comment #7, is it due to your erroneous device tree settings?
thanks
Hi JerryChang,
Did you know what is problem with my statement above?
I can’t get the dev/video file!
Is it due to my erroneous device tree settings?
Please help me,thanks a lot!
Because my captured HDMI is 1920X1080P50 So I set the default_timing is V4L2_DV_BT_CEA_1920X1080P50 ,in such situation . the 358743 module only enable 3 csi lanes output . and my device tree configure to 4 bus-lanes . It seems that fault cause PXL_SOF failure . when I change to V4L2_DV_BT_CEA_1920X1080P60 then it worked .
hi askariz0503:
Congratulations you have successfully transplanted tc358743 to L4T28.2.1, you said the source code, upload to the github download, please upload it ?, please give me a link.