When are the strapping pins sampled on the TX2?

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Hello,

I’m having problems getting the TX2 module to show boot messages on UART1. I’ve removed the SN74LVC2T45 level translator on UART1_TX and UART0_RTS, but the board still enters recovery mode regardless.

SLEEP on pin E2 is not connected in the schematic. RSVD_D8 is not connected in our schematic.

From what I see with a scope, UART1_TX and UART0_RTS are low prior to CARRIER_PWR_ON getting asserted. Which agrees with that I see in figure 41 of the DG.

I’d like to be sure the state of the all strapping pins are correct with a scope when the TX2 samples them. What external signal (e.g. CARRIER_PWR_ON) can be used to determine when they get sampled by the TX2, and if there is no external signal available at sample time, what signal with a time offset could possibly be used?

Thanks,

Steve

2

Hi, UART0_RTS should be high during power on as there is PU in module for it. Is there any other connection on this pin on your board?

3

Do you have an answer to Steve’s original question? When are the strapping pins sampled? Is it safe to drive the pins after CARRIER_PWR_ON is high? Or after RESET_OUT#? We are trying to establish a safe power-on sequence for our custom carrier.

4

The root cause is the level shift you used does not fit the request of guide and so affect the strap pins status during power-on. So the more important thing is to use appropriate level shift in next design, or just use same one of devkit. To mask external strapping setting is just a workaround.