Dear all,
My camera driver have been working well with L4T R28.1.0(Jetpack3.1) and L4T R28.2.0(Jetpack3.2) but it could not work with L4T R28.2.1 that now is updated to Jetpack3.2. I did some modification in order to add UYVY format to original driver as below
camera_common.c
static const struct camera_common_colorfmt camera_common_color_fmts[] = {
{
MEDIA_BUS_FMT_SRGGB12_1X12,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_SRGGB12,
},
{
MEDIA_BUS_FMT_SRGGB10_1X10,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_SRGGB10,
},
{
MEDIA_BUS_FMT_SBGGR10_1X10,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_SBGGR10,
},
{
MEDIA_BUS_FMT_SRGGB8_1X8,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_SRGGB8,
},
/*
* The below two formats are not supported by VI4,
* keep them at the last to ensure they get discarded
*/
/*{
MEDIA_BUS_FMT_XRGGB10P_3X10,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_XRGGB10P,
},
{
MEDIA_BUS_FMT_XBGGR10P_3X10,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_XRGGB10P,
},*/
{
MEDIA_BUS_FMT_UYVY8_2X8,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_UYVY,
},
{
MEDIA_BUS_FMT_UYVY8_1X16,
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_UYVY,
},
};
My dtb
#include "t18x-common-platforms/tegra186-quill-camera-e3322-a00.dtsi"
#define CAM0_RST_L TEGRA_MAIN_GPIO(R, 5)
#define CAM0_PWDN TEGRA_MAIN_GPIO(R, 0)
#define CAM1_RST_L TEGRA_MAIN_GPIO(R, 1)
#define CAM1_PWDN TEGRA_MAIN_GPIO(L, 6)
/ {
/* all cameras are disabled by default */
host1x {
vi@15700000 {
num-channels = <3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_vi_in0: endpoint {
csi-port = <0>;
bus-width = <4>;
remote-endpoint = <&e3326_csi_out0>;
};
};
port@1 {
reg = <1>;
e3326_vi_in1: endpoint {
csi-port = <2>;
bus-width = <4>;
remote-endpoint = <&e3326_csi_out1>;
};
};
port@2 {
reg = <2>;
e3326_vi_in2: endpoint {
csi-port = <4>;
bus-width = <4>;
remote-endpoint = <&e3326_csi_out2>;
};
};
};
};
nvcsi@150c0000 {
num-channels = <3>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_csi_in0: endpoint@0 {
csi-port = <0>;
bus-width = <4>;
remote-endpoint = <&e3326_ov10635_out0>;
};
};
port@1 {
reg = <1>;
e3326_csi_out0: endpoint@1 {
remote-endpoint = <&e3326_vi_in0>;
};
};
};
};
channel@1 {
reg = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_csi_in1: endpoint@2 {
csi-port = <2>;
bus-width = <4>;
remote-endpoint = <&e3326_ov10635_out1>;
};
};
port@1 {
reg = <1>;
e3326_csi_out1: endpoint@3 {
remote-endpoint = <&e3326_vi_in1>;
};
};
};
};
channel@2 {
reg = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_csi_in2: endpoint@4 {
csi-port = <4>;
bus-width = <4>;
remote-endpoint = <&e3326_ov10635_out2>;
};
};
port@1 {
reg = <1>;
e3326_csi_out2: endpoint@5 {
remote-endpoint = <&e3326_vi_in2>;
};
};
};
};
};
};
i2c@3180000 {
ov10635_a@30 {
compatible = "nvidia,ov10635";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
/* mclk-index indicates the index of the */
/* mclk-name with in the clock-names array */
clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
clock-frequency = <24000000>;
reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
/* I2C device address */
reg = <0x30>;
/* V4L2 device node location */
devnode = "video0";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
vana-supply = <&en_vdd_cam_hv_2v8>;
vif-supply = <&en_vdd_cam>;
mode0 {
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_a";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_ov10635_out0: endpoint {
csi-port = <0>;
bus-width = <4>;
remote-endpoint = <&e3326_csi_in0>;
};
};
};
};
};
i2c@31c0000 {
ov10635_b@30 {
compatible = "nvidia,ov10635";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
/* mclk-index indicates the index of the */
/* mclk-name with in the clock-names array */
clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
clock-frequency = <24000000>;
reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
/* I2C device address */
reg = <0x30>;
/* V4L2 device node location */
devnode = "video1";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
vana-supply = <&en_vdd_cam_hv_2v8>;
vif-supply = <&en_vdd_cam>;
mode0 {
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_c";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_ov10635_out1: endpoint {
csi-port = <2>;
bus-width = <4>;
remote-endpoint = <&e3326_csi_in1>;
};
};
};
};
};
i2c@31e0000 {
ov10635_c@30 {
compatible = "nvidia,ov10635";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
/* mclk-index indicates the index of the */
/* mclk-name with in the clock-names array */
clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
clock-frequency = <24000000>;
reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
/* I2C device address */
reg = <0x30>;
/* V4L2 device node location */
devnode = "video2";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
avdd-reg = "vana";
iovdd-reg = "vif";
vana-supply = <&en_vdd_cam_hv_2v8>;
vif-supply = <&en_vdd_cam>;
mode0 {
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_e";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
pixel_t = "bayer_bggr";
readout_orientation = "90";
line_length = "2688";
inherent_gain = "1";
mclk_multiplier = "6.67";
pix_clk_hz = "160000000";
min_gain_val = "1.0";
max_gain_val = "16";
min_hdr_ratio = "1";
max_hdr_ratio = "64";
min_framerate = "1.816577";
max_framerate = "30";
min_exp_time = "34";
max_exp_time = "550385";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
e3326_ov10635_out2: endpoint {
csi-port = <4>;
bus-width = <4>;
remote-endpoint = <&e3326_csi_in2>;
};
};
};
};
};
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <4>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <160000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. “rear” or “front”.
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module0 {
badge = "e3326_front_P5V27C";
position = "rear";
orientation = "1";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ov10635 2-0030";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/ov10635_c@30";
status = "okay";
};
drivernode1 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e3326_rear_lens_ov10635@P5V27C/";
};
};
module1 {
badge = "e3326_left_P5V27C";
position = "left";
orientation = "1";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ov10635 1-0030";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@31c0000/ov10635_c@30";
status = "okay";
};
drivernode1 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e3326_left_lens_ov10635@P5V27C/";
};
};
module2 {
badge = "e3326_right_P5V27C";
position = "right";
orientation = "1";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ov10635 3-0030";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@31e0000/ov10635_c@30";
status = "okay";
};
drivernode1 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_lens";
proc-device-tree = "/proc/device-tree/e3326_right_lens_ov10635@P5V27C/";
};
};
};
};
};
I could see /dev/video0, /dev/video1 and /dev/video2 as well. But when I tried to run rendering camera preview, it displayed as below
gst-launch-1.0 v4l2src device=/dev/video0 ! 'video/x-raw,width=1280,height=720,format=(string)UYVY' ! nvvidconv ! 'video/x-raw(memory:NVMM),format=(string)NV12' ! nvoverlaysink
Setting pipeline to PAUSED ...
Pipeline is live and does not need PREROLL ...
Setting pipeline to PLAYING ...
ERROR: from element /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: Internal data flow error.
Additional debug info:
gstbasesrc.c(2948): gst_base_src_loop (): /GstPipeline:pipeline0/GstV4l2Src:v4l2src0:
streaming task paused, reason not-negotiated (-4)
Execution ended after 0:00:00.000201985
Setting pipeline to PAUSED ...
Setting pipeline to READY ...
Setting pipeline to NULL ...
Freeing pipeline ...
More details
v4l2-ctl --all
Driver Info (not using libv4l2):
Driver name : tegra-video
Card type : vi-output, ov10635 2-0030
Bus info : platform:15700000.vi:0
Driver version: 4.4.38
Capabilities : 0x84200001
Video Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04200001
Video Capture
Streaming
Extended Pix Format
Priority: 2
Video input : 0 (Camera 0: no power)
Format Video Capture:
Width/Height : 1280/720
Pixel Format : 'UYVY'
Field : None
Bytes per Line : 2560
Size Image : 1843200
Colorspace : sRGB
Transfer Function : Default
YCbCr Encoding : Default
Quantization : Default
Flags :
Camera Controls
frame_length (int) : min=0 max=32767 step=1 default=2560 value=2560 flags=slider
coarse_time (int) : min=0 max=0 step=1 default=0 value=0 flags=slider
coarse_time_short (int) : min=0 max=0 step=1 default=0 value=0 flags=slider
group_hold (intmenu): min=0 max=1 default=0 value=0
hdr_enable (intmenu): min=0 max=1 default=0 value=0
error 22 getting ext_ctrl EEPROM Data
otp_data (str) : min=0 max=0 step=2 value='' flags=read-only, has-payload
fuse_id (str) : min=0 max=0 step=2 value='' flags=read-only, has-payload
gain (int) : min=0 max=0 step=1 default=0 value=0 flags=slider
bypass_mode (intmenu): min=0 max=1 default=0 value=0
override_enable (intmenu): min=0 max=1 default=0 value=0
height_align (int) : min=1 max=16 step=1 default=1 value=1
size_align (intmenu): min=0 max=2 default=0 value=0
write_isp_format (int) : min=1 max=1 step=1 default=1 value=1
sensor_signal_properties (u32) : min=0 max=4294967295 step=1 default=0 [30][10] flags=read-only, has-payload
sensor_image_properties (u32) : min=0 max=4294967295 step=1 default=0 [30][5] flags=read-only, has-payload
sensor_control_properties (u32) : min=0 max=4294967295 step=1 default=0 [30][14] flags=read-only, has-payload
sensor_dv_timings (u32) : min=0 max=4294967295 step=1 default=0 [30][6] flags=read-only, has-payload
sensor_modes (int) : min=0 max=30 step=1 default=30 value=1 flags=read-only
v4l2-compliance -d /dev/video0
Driver Info:
Driver name : tegra-video
Card type : vi-output, ov10635 2-0030
Bus info : platform:15700000.vi:0
Driver version: 4.4.38
Capabilities : 0x84200001
Video Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04200001
Video Capture
Streaming
Extended Pix Format
Compliance test for device /dev/video0 (not using libv4l2):
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second video open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 1 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Test input 0:
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
fail: v4l2-test-controls.cpp(624): did not check against size
test VIDIOC_G/S/TRY_EXT_CTRLS: FAIL
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 1 Private Controls: 15
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
fail: v4l2-test-formats.cpp(427): unknown pixelformat 59565955 for buftype 1
test VIDIOC_G_FMT: FAIL
test VIDIOC_TRY_FMT: OK (Not Supported)
test VIDIOC_S_FMT: OK (Not Supported)
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
fail: v4l2-test-buffers.cpp(571): q.has_expbuf(node)
test VIDIOC_EXPBUF: FAIL
Test input 0:
Total: 42, Succeeded: 39, Failed: 3, Warnings: 0
Thanks and Best Regards,
Vu Nguyen