use PCIe to communicate between two Xaviers: ep reports "UPHY init failed for PCIe EP: -22"

I’m trying to use PCIe to communication between two xaviers. One is in the default mode (root complex). Another is configured as endpoint mode.

Hardware setup:
Use cables to connect two xaviers through PCIE slot:

  • RX and TX are swapped in the cable
  • In the picture below, only PERST(A11) is connected between two xaviers
  • [img]https://www.diigo.com/file/image/bbddedcpzesspscreozdqradbae/webwxgetmsgimg+%2811%29.jpg?k=2906eaa323e40c803f4335fb941fdf31[/img]

Software changes of ep xavier:

  • Remove C5 root complex in device tree. (PS: I delete all the stuffs related to ep@141a0000 in device tree)
  • Enable C5 end point in device tree. (I can see the probe message in dmesg)
  • Disable pex-refclk-sel-low and enable pex-refclk-sel-high

Startup process:

  1. Powerup endpoint xavier
  2. Powerup complex root xavier

Dmesg information from endpoint xavier:UPHY init failed for PCIe EP: -22


The error is from the return of tegra_bpmp_send_receive() in bpmp_send_uphy_message().

Dmesg information from root complex xavier:

I do it in the same way (c5 rc–>disabled, ep–>okay, refclk–>high)except PERST pin, but the host can not recognize the client and there is no log in dmesg. Do the ep log is added by yourself? Thanks

“pcie-ep world 5” is added by myself. The error message at the bottom isn’t my code.

And you mean you didn’t connect PERST between two Xaviers?

I connect all pcie x16 pins together between two xaviers. I can not find error message at the bottom and the host can not find client with lspci.
I add message to tegra_pcie_dw_ep_probe function, but it doesn’t print. Where do you add message? Thanks

Please set BIT:12 of ODM data to enable PCIe EndPoint mode
ODMDATA=0x9191000;

The file you need to change should be “p2972-0000.conf.common”

Otherwise, bpmp would not change.

Thanks Wayne. It works. But what does bpmp stand for? Why I need to change it to enable endpoint mode?

Hi WayneWWW

Can you send me the link the pcb layout orcad layout & cadence 17.2 for PCIE endpoint.

602-83317-1000-A01.pdf

Hi,
Can I buy the PCIe cable to connect the two Jetson Xaviers instead of making it myself ?

Hi zhuce_cgf,
Where did you get the PCIe jumper cable?