I’ve made some progress on the port but I’ve run into a major stumbling block. When attempting to start capture I am getting an error as the system tries to dynamically parse the device tree. I updated from csi-port to port-index and as far as I’m aware that is the only update I needed to make in the .dts file. Is there anything else I’m missing that would cause issues when dynamically parsing the file?
/*
* tegra186-quill-p3310-c03-00-base.dts Quill C03 Board
*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "tegra186-quill-p3310-1000-a00-00-base.dts"
/ {
nvidia,dtsfilename = __FILE__;
nvidia,dtbbuildtime = __DATE__, __TIME__;
nvidia,fastboot-usb-vid = <0x0955>;
nvidia,fastboot-usb-pid = <0xee16>;
pinmux@2430000 {
common {
gpio_edp2_pp5 {
status = "okay";
};
gpio_edp3_pp6 {
status = "okay";
};
};
};
gpio@2200000 {
sdmmc-wake-support-input {
status = "okay";
};
sdmmc-wake-support-output {
status = "okay";
};
};
fixed-regulators {
regulator@1 {
gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 6) 0>;
};
};
sdhci@3400000 {
cd-gpios = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 5) 0>;
nvidia,cd-wakeup-capable;
};
i2c@3160000 {
ina3221x@40 {
channel@0 {
ti,shunt-resistor-mohm = <10>;
};
channel@1 {
ti,shunt-resistor-mohm = <10>;
};
};
ina3221x@41 {
channel@0 {
ti,shunt-resistor-mohm = <20>;
};
channel@1 {
ti,shunt-resistor-mohm = <10>;
};
channel@2 {
ti,rail-name = "VDD_SYS_DDR";
ti,shunt-resistor-mohm = <10>;
};
};
};
i2c@c240000 {
bmi160@69 {
compatible = "bmi,bmi160";
reg = <0x69>;
interrupt-parent = <&tegra_aon_gpio>;
interrupts = <TEGRA_AON_GPIO(AA, 2) 0x01>;
accelerometer_matrix = [01 00 00 00 01 00 00 00 01];
gyroscope_matrix = [01 00 00 00 01 00 00 00 01];
accelerometer_delay_us_min = <1250>;
gyroscope_delay_us_min = <1250>;
vdd-supply = <&spmic_sd3>;
vdd_IO-supply = <&spmic_sd3>;
status = "okay";
};
};
mttcan@c310000 {
status = "okay";
gpio_can_stb = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
gpio_can_en = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
mram-params = <0 16 16 8 8 8 16 16 16>;
tx-config = <8 8 0 64>;
rx-config = <64 64 64>;
};
mttcan@c320000 {
status = "okay";
gpio_can_stb = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 6) GPIO_ACTIVE_HIGH>;
gpio_can_en = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
mram-params = <0 16 16 8 8 8 16 16 16>;
tx-config = <8 8 0 64>;
rx-config = <64 64 64>;
};
ahci-sata@3507000 {
gpios = <&spmic 7 0>;
};
pcie-controller@10003000 {
pci@1,0 {
nvidia,num-lanes = <4>;
nvidia,disable-clock-request;
};
pci@2,0 {
nvidia,num-lanes = <0>;
};
pci@3,0 {
nvidia,num-lanes = <1>;
};
};
xhci@3530000 {
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
phy-names = "utmi-0", "utmi-1", "usb3-0";
};
pinctrl@3520000 {
pinmux {
usb3-std-A-port2 {
nvidia,lanes = "usb3-0";
};
};
};
bluedroid_pm {
bluedroid_pm,reset-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(H, 5) 0>;
};
bpmp_i2c {
spmic@3c {
pinmux@0 {
pin_gpio2 {
status = "disabled";
};
pin_gpio3 {
status = "disabled";
};
pin_gpio7 {
drive-push-pull = <1>;
};
};
regulators {
ldo0 {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
};
ldo6 {
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
regulator-boot-on;
regulator-always-on;
};
ldo7 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
ldo8 {
regulator-name = "dvdd-pex";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
};
};
};
/*
* NOTE: the following is manually added
*/
/* CSI subdevice */
i2c@3180000 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
tc358840@0f {
status = "okay";
compatible = "toshiba,tc358840";
reg = <0x0f>;
devnode = "video0";
/* Power Supply */
vdig-supply = <&en_vdd_cam_1v2>;
vif-supply = <&en_vdd_cam>;
// clocks = <&hdmi_osc>;
// clock-names = "refclk";
reset-gpios = <&tegra_main_gpio TEGRA_MAIN_GPIO(R, 5) GPIO_ACTIVE_LOW>;
interrupt-parent = <&tegra_main_gpio>;
interrupts = <TEGRA_MAIN_GPIO(R, 0) IRQ_TYPE_LEVEL_HIGH>;
csi_port = <3>;
refclk_hz = <48000000>; /* 40 - 50 MHz */
ddc5v_delay = <1>; /* 50 ms */
enable_hdcp = <0>;
// line rate 1 Gbit / CSI lane
lineinitcnt = <8000>;
lptxtimecnt = <7>;
tclk_headercnt = <0x00320206>;
tclk_trailcnt = <0x00040005>;
ths_headercnt = <0x00190008>;
twakeup = <0x00004E20>;
tclk_postcnt = <0x0000000A>;
ths_trailcnt = <0x0010000B>;
hstxvregcnt = <0x00000020>;
/* PLL */
/* Bps per lane is (refclk_hz / pll_prd + 1) * pll_fbd + 1 */
pll_prd = <5>;
pll_fbd = <125>;
port {
tc358840_out0: endpoint {
vc-id = <0>;
remote-endpoint = <&hdmi_to_csi_in0>;
data-lanes = <1 2 3 4>;
clock-lanes = <0>;
// clock-noncontinuous;
link-frequencies = /bits/ 64 <297000000>;
};
};
};
tc358840@1f {
status = "okay";
compatible = "toshiba,tc358840";
reg = <0x1f>;
devnode = "video1";
/* Power Supply */
vdig-supply = <&en_vdd_cam_1v2>;
vif-supply = <&en_vdd_cam>;
reset-gpios = <&tegra_main_gpio TEGRA_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW>;
interrupt-parent = <&tegra_main_gpio>;
interrupts = <TEGRA_MAIN_GPIO(N, 2) IRQ_TYPE_LEVEL_HIGH>;
csi_port = <1>;
refclk_hz = <48000000>; /* 40 - 50 MHz */
ddc5v_delay = <1>; /* 50 ms */
enable_hdcp = <0>;
// line rate 1 Gbit / CSI lane
lineinitcnt = <8000>;
lptxtimecnt = <7>;
tclk_headercnt = <0x00320206>;
tclk_trailcnt = <0x00040005>;
ths_headercnt = <0x00190008>;
twakeup = <0x00004E20>;
tclk_postcnt = <0x0000000A>;
ths_trailcnt = <0x0010000B>;
hstxvregcnt = <0x00000020>;
/* PLL */
/* Bps per lane is (refclk_hz / pll_prd + 1) * pll_fbd + 1 */
pll_prd = <5>;
pll_fbd = <125>;
port {
tc358840_out1: endpoint {
vc-id = <1>;
remote-endpoint = <&hdmi_to_csi_in1>;
data-lanes = <1 2 3 4>;
clock-lanes = <0>;
// clock-noncontinuous;
link-frequencies = /bits/ 64 <297000000>;
};
};
};
};
host1x {
/* Delete existing VI node to avoid conflicts */
/delete-node/ vi;
/* CSI related */
vi@15700000 {
// compatible = "nvidia,tegra186-gp-vi";
compatible = "nvidia,tegra186-vi";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
num-channels = <2>;
avdd_dsi_csi-supply = <&spmic_sd1>;
/* COPY FROM BASE DT: tegra186-soc-base.dtsi ------------------- */
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VE>;
reg = <0x0 0x15700000 0x0 0x00100000>;
interrupts = <0 201 0x04
0 202 0x04
0 203 0x04>;
resets = <&tegra_car TEGRA186_RESET_VI>,
<&tegra_car TEGRA186_RESET_TSCTNVI>;
reset-names = "vi", "tsctnvi";
clocks = <&tegra_car TEGRA186_CLK_VI>,
<&tegra_car TEGRA186_CLK_NVCSI>,
<&tegra_car TEGRA186_CLK_NVCSILP>;
clock-names = "vi", "nvcsi", "nvcsilp";
#stream-id-cells = <1>;
/* ------------------------------------------------------------- */
ports {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
/* TX2 interconnect ports */
port@0 {
status = "okay";
reg = <0>;
hdmi_to_csi_vi_in0: endpoint {
status = "okay";
vc-id = <0>;
port-index = <0>;
bus-width = <8>; //<8>
// bus-width = <1>;
remote-endpoint = <&hdmi_2_csi_out0>;
};
};
port@1 {
status = "okay";
reg = <1>;
hdmi_to_csi_vi_in1: endpoint {
status = "okay";
vc-id = <1>;
port-index = <4>;
bus-width = <4>;
remote-endpoint = <&hdmi_2_csi_out1>;
};
};
};
};
nvcsi@150c0000 {
compatible = "nvidia,tegra186-nvcsi";
status = "okay";
num-channels = <2>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
status = "okay";
reg = <0>;
ports {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
status = "okay";
reg = <0>;
hdmi_to_csi_in0: endpoint@0 { /* from I2C */
status = "okay";
port-index = <0>;
bus-width = <8>;
remote-endpoint = <&tc358840_out0>; /* to I2C */
};
};
port@1 {
status = "okay";
reg = <1>;
hdmi_2_csi_out0: endpoint@1 { /* from VI */
status = "okay";
remote-endpoint = <&hdmi_to_csi_vi_in0>; /* to VI */
};
};
};
};
channel@1 {
status = "okay";
reg = <1>;
ports {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
status = "okay";
reg = <0>;
hdmi_to_csi_in1: endpoint@2 { /* from I2C */
status = "okay";
port-index = <4>;
bus-width = <4>;
remote-endpoint = <&tc358840_out1>; /* to I2C */
};
};
port@1 {
status = "okay";
reg = <1>;
hdmi_2_csi_out1: endpoint@3 { /* from VI */
status = "okay";
remote-endpoint = <&hdmi_to_csi_vi_in1>; /* to VI */
};
};
};
};
};
};
mipical {
status = "okay";
};
fixed-regulators {
/* HDMI2CSI / FPGA MADI BOARD REGULATORS */
en_vdd_sys:regulator@118 {
regulator-boot-on;
regulator-always-on;
};
en_vdd_cam:regulator@2 {
regulator-boot-on;
regulator-always-on;
};
en_vdd_cam_1v2:regulator@12 {
regulator-boot-on;
regulator-always-on;
};
/* FPGA MADI BOARD REGULATOR */
en_avdd_disp_3v3:regulator@8 {
regulator-boot-on;
regulator-always-on;
};
};
/*** HDMI2CSI ***/
/* set camera gpio direction to output */
pinmux@2430000 {
common {
/*
* Pull down the INT pin of the TC358840 (HDMI IN A) while
* in reset in order to set i2c address 0x0F.
*/
qspi_sck_pr0 {
nvidia,pins = "qspi_sck_pr0";
nvidia,function = "rsvd1";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
/*
* Pull up the INT pin of the TC358840 (HDMI IN B) while
* in reset in order to set i2c address 0x1F.
*/
gpio_cam3_pn2 {
nvidia,pins = "gpio_cam3_pn2";
nvidia,function = "rsvd2";
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
};
/* set camera gpio direction to output */
gpio@2200000 {
camera-control-output-low {
status = "okay";
gpio-hog;
output-low;
gpios = <TEGRA_MAIN_GPIO(R, 5) 0
TEGRA_MAIN_GPIO(R, 1) 0>;
label = "cam0-rst", "cam1-rst";
};
camera-control-input {
status = "okay";
gpio-hog;
input;
gpios = <TEGRA_MAIN_GPIO(R, 0) 0
TEGRA_MAIN_GPIO(N, 2) 0>;
label = "cam0-int", "cam1-int";
};
};
};