Hi,
I’m trying to configure nano I2S audio output as below:
aud_mclk
I2S3_LRCK
I2S3_SDATA_IN
I2S3_SDATA_OUT
I2S3_SCLK
I’ve done some dtsi modifications, compile to DTB and signed, flash to mmcblk0p10.
Build u-boot and flash via command
sudo ./flash.sh -k LNX jetson-nano-qspi-sd mmcblk0p1
Got aud_mclk working with 12.2MHz.
Test with command, but still not working.
speaker-test -c2 -twav -D plughw:CARD=tegrasndt210ref,DEV=0
Could anyone give me a hint? Many thanks.
diff --git a/u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h b/u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h
index 49df131..f050f5d 100644
--- a/u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h
+++ b/u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h
@@ -70,7 +70,6 @@ static const struct tegra_gpio_config p3450_porg_gpio_inits[] = {
GPIO_INIT(Z, 0, IN),
GPIO_INIT(Z, 2, IN),
GPIO_INIT(Z, 3, OUT0),
- GPIO_INIT(BB, 0, IN),
GPIO_INIT(CC, 4, IN),
GPIO_INIT(CC, 7, OUT1),
GPIO_INIT(DD, 0, IN),
@@ -116,7 +115,7 @@ static const struct pmux_pingrp_config p3450_porg_pingrps[] = {
PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC3_CLK_PE4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
@@ -216,7 +215,7 @@ static const struct pmux_pingrp_config p3450_porg_pingrps[] = {
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
- PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AUD_MCLK_PBB0, AUD, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(DVFS_CLK_PBB2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
diff --git a/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0000-a02.dtsi b/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0000-a02.dtsi
index 6acdc55..530ab08 100755
--- a/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0000-a02.dtsi
+++ b/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0000-a02.dtsi
@@ -20,13 +20,13 @@
#include <dt-bindings/gpio/tegra-gpio.h>
/ {
gpio: gpio@6000d000 {
gpio-init-names = "default";
gpio-init-0 = <&gpio_default>;
gpio_default: default {
gpio-input = <
- TEGRA_GPIO(BB, 0)
TEGRA_GPIO(B, 4)
TEGRA_GPIO(B, 5)
TEGRA_GPIO(B, 6)
diff --git a/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a02.dtsi b/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a02.dtsi
index b226e1a..03916f8 100755
--- a/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a02.dtsi
+++ b/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a02.dtsi
@@ -29,6 +29,14 @@
pinmux_default: common {
/* SFIO Pin Configuration */
+ aud_mclk_pbb0 {
+ nvidia,pins = "aud_mclk_pbb0";
+ nvidia,function = "aud";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,function = "cldvfs";
@@ -58,7 +66,7 @@
nvidia,function = "i2s3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
dmic2_dat_pe3 {
@@ -591,14 +599,6 @@
};
/* GPIO Pin Configuration */
- aud_mclk_pbb0 {
- nvidia,pins = "aud_mclk_pbb0";
- nvidia,function = "rsvd1";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- };
-
spi2_mosi_pb4 {
nvidia,pins = "spi2_mosi_pb4";
nvidia,function = "rsvd2";
and check…
~# cat /sys/kernel/debug/pinctrl/700008d4.pinmux/pinmux-pins
pin 218 (DVFS_CLK PBB2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 219 (GPIO_X1_AUD PBB3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 220 (GPIO_X3_AUD PBB4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 224 (HDMI_CEC PCC0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 225 (HDMI_INT_DP_HPD PCC1): (MUX UNCLAIMED) tegra-gpio:225
pin 226 (SPDIF_OUT PCC2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 227 (SPDIF_IN PCC3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
and
~# cat /sys/kernel/debug/pinctrl/700008d4.pinmux/pinmux-functions | grep -i i2s3
function: i2s3, groups = [ dmic1_clk_pe0 dmic1_dat_pe1 dmic2_clk_pe2 dmic2_dat_pe3 ]
root@efrd-desktop:~# cat /sys/kernel/debug/pinctrl/pinctrl-handles | grep i2s3
type: MUX_GROUP controller 700008d4.pinmux group: dmic1_clk_pe0 (52) function: i2s3 (24)
type: MUX_GROUP controller 700008d4.pinmux group: dmic1_dat_pe1 (53) function: i2s3 (24)
type: MUX_GROUP controller 700008d4.pinmux group: dmic2_clk_pe2 (54) function: i2s3 (24)
type: MUX_GROUP controller 700008d4.pinmux group: dmic2_dat_pe3 (55) function: i2s3 (24)
and
root@efrd-desktop:~# cat /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
A: 0:0 64 40 40 04 00 00 000000
B: 0:1 f0 00 00 00 00 00 000000
C: 0:2 1f 00 00 18 00 00 000000
D: 0:3 00 00 00 00 00 00 000000
E: 1:0 40 00 00 00 00 00 000000
F: 1:1 00 00 00 00 00 00 000000
G: 1:2 0c 00 00 0c 00 00 000000
H: 1:3 fd 99 00 60 00 00 000000
I: 2:0 07 07 02 00 00 00 000000
J: 2:1 f0 00 00 00 00 00 000000
K: 2:2 00 00 00 00 00 00 000000
L: 2:3 00 00 00 00 00 00 000000
M: 3:0 00 00 00 00 00 00 000000
N: 3:1 00 00 00 00 00 00 000000
O: 3:2 00 00 00 00 00 00 000000
P: 3:3 00 00 00 00 00 00 000000
Q: 4:0 00 00 00 00 00 00 000000
R: 4:1 00 00 00 00 00 00 000000
S: 4:2 a0 80 00 20 00 00 000000
T: 4:3 01 01 00 00 00 00 000000
U: 5:0 00 00 00 00 00 00 000000
V: 5:1 03 00 00 00 00 00 000000
W: 5:2 00 00 00 00 00 00 000000
X: 5:3 78 08 08 70 00 60 606000
Y: 6:0 06 00 00 02 00 00 000000
Z: 6:1 0f 08 08 05 00 06 020600
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000
CC: 7:0 92 80 80 10 00 12 121200
DD: 7:1 01 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000