How to disable SPI2 and enable UART7

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
1

We want to enable UART7 for a test on xavier,and we noticed that there are some combination functions(it is used as SPI2),
how can we make UART7 work?

2

Now,we have disabled SIP2 and enabled UART7,dmesg shows like this:
[ 0.012602] console [tty0] enabled
[ 1.813205] 3100000.serial: ttyTHS0 at MMIO 0x3100000 (irq = 50, base_baud = 0) is a TEGRA_UART
[ 1.815359] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 51, base_baud = 0) is a TEGRA_UART
[ 1.817064] 3140000.serial: ttyTHS4 at MMIO 0x3140000 (irq = 52, base_baud = 0) is a TEGRA_UART
[ 1.818544] 3150000.serial: ttyTHS5 at MMIO 0x3150000 (irq = 53, base_baud = 0) is a TEGRA_UART
[ 1.820559] c290000.serial: ttyTHS6 at MMIO 0xc290000 (irq = 54, base_baud = 0) is a TEGRA_UART
[ 1.822127] 3170000.serial: ttyTHS7 at MMIO 0x3170000 (irq = 55, base_baud = 0) is a TEGRA_UART
[ 4.361697] console [ttyTCU0] enabled

We tried /dev/ttyTHS5,/dev/ttyTHS6,/dev/ttyTHS7,but there is no data on UART7_TX pin.

3

hello sclsdhlr,

please access Xavier Series (SoC) Technical Reference Manual via Jetson Download Center,
please refer to [9.5.4 PinMux Registers]-> [AO PAD Control Registers] session.

you should configure below registers, modify bit [1:0] to 0x1 will select UARTG function.

PADCTL_AO_SPI2_MOSI_0 | offset: 0x28
PADCTL_AO_SPI2_CS0_0  | offset: 0x38
PADCTL_AO_SPI2_SCK_0  | offset: 0x48
PADCTL_AO_SPI2_MISO_0 | offset: 0x50

you may working with debug tools, such as dev2mem to write register directly,
Or, you may check Jetson AGX Xavier MB1 Platform Configuration chapter for the steps to update the pinmux config.
thanks

4

It works! Thank you JerryChang.

5

i changed this registers
PADCTL_AO_SPI2_MOSI_0 | offset: 0x28
PADCTL_AO_SPI2_CS0_0 | offset: 0x38
PADCTL_AO_SPI2_SCK_0 | offset: 0x48
PADCTL_AO_SPI2_MISO_0 | offset: 0x50

anything else？

i use the devmem，the register has changed but ttyTHS7 dosent create, thankyou