We are designing a product needed some GPIOs,PWM x 4,SPI x 1 and I2C x 1. We must figure out these interfaces. But so many processors in the Paker SoC make us difficult to code. Here we lists some questions about the communication between SPE and CPU complex.
(1) TX2 module has 8x50 pins, and is that a pin only connect to a special processor, or shared by processors? How can I figure out it?
(2) We know SPE runs FreeRTOS, and CCPLEX runs linux, how can they communication?
(3) Could SPE’s GPIO,SPI,I2C,PWM be used by Linux? For example, in factory, if we just need verify the HW, can we 1)easily operate the interfaces by Linux. 2)After upgrade to final FW, the interfaces turn to be operated by RTOS.
(4) From TECHNICAL REFERENCE MANUAL for the NVIDIA Parker Series SoC, Chapter 18.23: The AON cluster implements one PWM. That means SPE support one PWM controller(8 PWM output) or only support 1 PWM output?
Any help would be very appreciated.