Hello,
I have connected a mipi-csi-2 12 Megapixels RAW12 camera sensor to my Jetson TX2, and it works perfectly with the following gstreamer pipeline that does not use the ISP
gst-launch-1.0 v4l2src device=/dev/video0 ! video/x-raw,format=GRAY8,height=3008,framerate=234/10 ! nvvidconv ! nvjpegenc ! multifilesink location=%05d.jpg max-files=5
Note: the sensor sends RAW12 pixels, but I have instructed the VI to truncate the pixels to 8 bits when asked to produce GRAY8.
However, if I try to use the ISP, with the following command
gst-launch-1.0 nvcamerasrc ! video/x-raw\(memory:NVMM\),width=4112,height=3008,framerate=1/1 ! fakesink
it stops immediately with the following kernel message :
[ 101.330342] tegra-vi4 15700000.vi: master error
In the Parker Manual, Master Error is documented as follows :
MASTER_ERR_STATUS: This status bit is set whenever there is any kind of Error situation [ISPBUFA_ERR,
NOTIFY_FIFO_OVERFLOW, ATOMP_PACKER_FIFO_OVFL, CSIMUX_FIFO_OVFL, HOST_PKTINJECT_STALL_ERR]
that occurs in VI & the corresponding MASK bit is set in INTERRUPT_MASK register.
I have tried ‘framerate=1/1’ above after having my pipeline crashing at 23/1 fps, but changing the framerate does not change the speed used to send individual frames.
I have added the following debugging messages after the ‘master error’ message
diff --git a/drivers/video/tegra/host/vi/vi4.c b/drivers/video/tegra/host/vi/vi4.c
index dcaa529..3d16a3a 100644
--- a/drivers/video/tegra/host/vi/vi4.c
+++ b/drivers/video/tegra/host/vi/vi4.c
@@ -90,6 +90,11 @@ static irqreturn_t nvhost_vi4_error_isr(int irq, void *dev_id)
if (r) {
host1x_writel(pdev, VI_CFG_INTERRUPT_STATUS_0, 1);
dev_err(&pdev->dev, "master error\n");
+ dev_err(&pdev->dev, "VI_CFG_INTERRUPT_STATUS_0 = %x\n", r);
+ if (r & 1) {
+ dev_err(&pdev->dev, "VI_ISPBUFA_ERROR_0 = %x\n", host1x_readl(pdev, VI_ISPBUFA_ERROR_0));
+ dev_err(&pdev->dev, "VI_NOTIFY_ERROR_0 = %x\n", host1x_readl(pdev, VI_NOTIFY_ERROR_0));
+ }
atomic_inc(&vi->overflow);
}
and I get the following info :
[ 113.639740] tegra-vi4 15700000.vi: master error
[ 113.644320] tegra-vi4 15700000.vi: VI_CFG_INTERRUPT_STATUS_0 = 3f000001
[ 113.650995] tegra-vi4 15700000.vi: VI_ISPBUFA_ERROR_0 = 1
[ 113.656462] tegra-vi4 15700000.vi: VI_NOTIFY_ERROR_0 = 0
In the Parker TRM, bit 0 of the VI_ISPBUFA_ERROR_0 register is documented as follows
FIFO_OVERFLOW: Set by Hardware when the ISPBUF's internal FIFO has overflowed. (Generally due
to clock speed mismatch b/w ISP and VI interfaces) Write 1 to clear. Also causes VI Master error.
Is there anything that can be done to solve that problem or is the TX2 ISP simply not able to accept a 12 Mpixels RAW12 image coming in at 4752 Mbps ?