Use of TX2 Watchdog peripheral - role of WDT_TIME_OUT input

I would like to use a hard watchdog with TX2 in an application where an external device could refresh such a watchdog timer. I’ve see that there are some linux drivers but I can’t find a clear descriptino of how to use the WDT_TIME_OUT hardware input.

Is there any document describing that?

Below document may help

https://android.googlesource.com/kernel/tegra/+/android-tegra-3.10/Documentation/watchdog/watchdog-api.txt

The WDT0 device node is /dev/watchdog0. The following user-space sample code shows opening, enabling, obtaining and specifiying the timeout value, and kicking the watchdog timer.

int fd, ret;
int timeout = 0;
 
/* open WDT0 device (WDT0 enables itself automatically) */
fd = open("/dev/watchdog0", O_RDWR);
if(fd < 0) {
    fprintf(stderr, "Open watchdog device failed!\n");
    return -1; 
}
/* WDT0 is counting now,check the default timeout value */
ret = ioctl(fd, WDIOC_GETTIMEOUT, &timeout);
if(ret) {
    fprintf(stderr, "Get watchdog timeout value failed!\n");
    return -1; 
}
fprintf(stdout, "Watchdog timeout value: %d\n", timeout);
 
/* set new timeout value 60s */
/* Note the value should be within [5, 1000] */
timeout = 60;
ret = ioctl(fd, WDIOC_SETTIMEOUT, &timeout);
if(ret) {
    fprintf(stderr, "Set watchdog timeout value failed!\n");
    return -1;
}
fprintf(stdout, "New watchdog timeout value: %d\n", timeout);  
 
/*Kick WDT0, this should be running periodically */
ret = ioctl(fd, WDIOC_KEEPALIVE, NULL);
if(ret) {
    fprintf(stderr, "Kick watchdog failed!\n");
    return -1;
}

Thank you for the documentation and code sample which help me at the user space in Linux.

However I still need to understand how to use the WDT_TIME_OUT# pin of the Jetson TX2 Module:

• TX2 OEM Product Design Guide shows this pin as an input, but driven high before CARRIER_PWR_ON active ???
• TX2 Pinmux Template shows this pin as output “WDT_RESET_OUTA” ???

Any idea?

What your purpose for this pin?

My purpose depends on the exact role of this pin of the TX2:

• Is it an output indicating that the TX2 resets because of a watchdog timeout?
• Is it an output indicating a watchdog refresh by user space?
• Is it an input that can simulate a watchdog refresh?
• Anything else?

My TX2 must be integrated on a carrier board were another component (PLD) is monitoring the complete system and provide watchdog funtionnality. I need to know how to integrate both.

• Is it an output indicating that the TX2 resets because of a watchdog timeout? Yes

At the moment there is no software configuration that can enable generation of WDT_RESET_OUT signal.
But the register PMC_IMPL_RST_REQ_CONFIG_0(0xc360114) can be written from BPMP.
Set the value using command
echo “mw 0xc360114 1” > /sys/kernel/debug/bpmp/debug/cons
Pinmux should be updated to configure WDT_RESET_OUT pin (SOC_GPIO23) as WDT_RESET_OUTA using the customer_pinmux.xlsm

WDT reset after this will pull the WDT_RESET_OUT signal low. But the system will reboot only when SYS_RESET_N is toggled.
So the external PLD will have to capture WDT_RESET_OUT signal going low and then drive SYS_RESET_N to reboot the system.

Thanks for the details!

hi,

i need to use the same watchdog function but with Python to jetson nano, but i don’t find the WDIOC_KEEPALIVE and WDIOC_SETTIMEOUT values.

Do you know how can i make ?
Thanks

1. If i want to use bpmp, how do i configure TX2?
   E.g Enable UART7, or connect debug connector(J10) to developer kit between TX2 and Host
   because i reference this post https://devtalk.nvidia.com/default/topic/1025679/jetson-tx2/how-to-enable-uart7-d8-d5-as-normal-uart-like-other-uart-uartc-c280000-/3 to enable uart7, but i use command

#: echo “mw 0xc360114 1” > /sys/kernel/debug/bpmp/debug/cons

return
bash: /sys/kernel/debug/bpmp/debug/cons: Permission denied

2. Can i modify dts or dtsi to achieve the same function?

thank you

Hi t.barrachina and martin_li,

Please open a new topic for your issue. Thanks.

Hi ShaneCCC,

I have a customised tx2 board which does not have the /dev/wathdog0 node. Is any other way to know if watchdog circuit is active or not. So that we can configure and test with the script mentioned.

Hi @siddharth2,
considering that you have a custom design is very hard to guess why you don’t have the /dev/wathdog0.
Did you customize the kernel?
Do you have a schematic excerpt of WD section?

The watchdog0 should be in the TX2 SOC chip and should be enable by default image.

hi:
I encountered the following problems using the above code 。
The new watchdog timeout value can only be set to 25. I want to set a smaller value. What should I do?

Any kernel message while set the timer?

tegra_wdt_t18x 30c0000.watchdog: Tegra WDT init timeout = 120 sec

in the watchdog node, you can set timeout as minimum 1sec

tegra_wdt:watchdog@30c0000 {
	
	timeout-sec = <1>;
	
};