After enable SPI1 by tegra-io utility in nano dev kit running on l4t32.3.1, I shortcut SPI_1_MOSI(J41 Pin 19) and SPI_1_MOSI(J41 Pin 21) and test by linux official spidev_test tool, it works.
But when I test the Nano dev kit SPI1 with a slave(stm32 Nucleo), the voltage of SPI_1_CS0(J41 Pin 124) is about -1.9V, and more or less 0V same as that of GND after use the above script "sudo ./spidev_test -D /dev/spidev0.0 -v -p “test spi1”. The slave and master can’t communicate through spi1. As we all known, the CS pin of SPI1 should high or low when transfer data, that is so weird.
Hi,
Signal to Jetson Nano devkit J41 pin 24 is SPI1_CS0_LS, this is a signal after level shifter.
The level shifter used is TXB0108RGYR, it’s designed to drive capacitive loads of up to 70 pF. The output drivers have low dc drive strength. If pullup or pulldown resistors are connected externally to the data I/Os, their values must be kept higher than 50 kΩ to ensure that they do not contend with the output drivers.
So please check if any strong pull on this pin when you use it, remove it should able to get a pure H or L logic.
After shortcut MOSI and MISO, we get the waves(below pic.) of SPI_1_SCK and SPI_1_CS0 of Jetson Nano dev kit with L4t32.3.1 by a logic analyzer. External Media
Seem the CLK is broken. How to make the SPI_1_SCK work normally?
We use the linux official spidev_test tool to test. We just need set a clock speed to the follow spi_ioc_transfer, and the clock should worked.
We made a mistake that a byte is sent what we intent to in a while loop prior to catching it in logic analyzer. But actually the loop not work, so we can’t catch the CLK and MOSI wave which we thought to be. After we start the logic analyzer first, it’s Okay for Nano dev kit spi1. External Media
Thanks