How to enable spi2 with R32.3.1

Karis · February 5, 2020, 2:27am

Hi,

I use nano with emmc and our carrierboard.
(tegra210-p3448-0002-p3449-0000-b00.dtb)

I would like to enable spi2.

Jetson Nano Signal Name 40 Pin Header Ball Name
SPI1_MOSI 37 SPI2_MOSI
SPI1_MISO 22 SPI2_MISO
SPI1_SCK 13 SPI2_SCK
SPI1_CS0* 18 SPI2_CS0
SPI1_CS1* 16 SPI2_CS1

I follwed this links below.

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%2520Linux%2520Driver%2520Package%2520Development%2520Guide%2Fhw_setup_jetson_io.html

https://devtalk.nvidia.com/default/topic/1068583/jetson-nano/jetpack-4-3-l4t-r32-3-1-released/post/5413341/#5413341

I ran sudo /opt/nvidia/jetson-io/jetson-io.py ,but nothing happened.

Thanks!

ShaneCCC · February 5, 2020, 2:46am

Did you add spidev like below? Have a reference to below link to modify the device tree for it.

https://elinux.org/Jetson/TX2_SPI

github.com

gtjoseph/jetson-nano-support/blob/l4t_32.2.1/spi/l4t-sources-kernel-hardware-nvidia-platform-t210-porg-spidev0-0.patch

diff --git a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0000-a02.dtsi b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0000-a02.dtsi
index 6acdc55..75e199d 100755
--- a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0000-a02.dtsi
+++ b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0000-a02.dtsi
@@ -50,10 +50,6 @@
 				TEGRA_GPIO(J, 7)
 				TEGRA_GPIO(G, 2)
 				TEGRA_GPIO(G, 3)
-				TEGRA_GPIO(C, 0)
-				TEGRA_GPIO(C, 1)
-				TEGRA_GPIO(C, 2)
-				TEGRA_GPIO(C, 3)
 				TEGRA_GPIO(C, 4)
 				TEGRA_GPIO(H, 2)
 				TEGRA_GPIO(H, 5)
diff --git a/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a02.dtsi b/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a02.dtsi
index b226e1a..68f451c 100755
--- a/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a02.dtsi
+++ b/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-a02.dtsi
@@ -825,7 +825,7 @@

This file has been truncated. show original

spi@xxxxx{
    ....
    ....
    ....
    linux,phandle = <0x80>;
    spi@0 {
      compatible = "spidev";
      reg = <0x0>;
      spi-max-frequency = <0x1312D00>;
      nvidia,enable-hw-based-cs;
      nvidia,cs-setup-clk-count = <0x1e>;
      nvidia,cs-hold-clk-count = <0x1e>;
      nvidia,rx-clk-tap-delay = <0x1f>;
      nvidia,tx-clk-tap-delay = <0x0>;
    }; 
 };

Karis · February 5, 2020, 3:27am

Hi ShaneCCC,

Thank you for your reply.

YES!

On R32.2.1 it’s work fine.
On R32.3.1 it doesn’t need to build u-boot.bin, so I don’t know how to do.

Thanks!

ShaneCCC · February 5, 2020, 3:31am

Have a reference to below topi.

https://devtalk.nvidia.com/default/topic/1062646

Karis · February 10, 2020, 3:33am

Hi ShaneCCC,

This is for R32.2.1 & tegra210-p3448-0000-p3449-0000-a02

It needs to build u-boot.bin.

Thanks!

ShaneCCC · February 10, 2020, 5:48am

Below link was on r32.3.1

https://github.com/rt-net/JetsonNano_DT_SPI/issues/9

Karis · February 10, 2020, 6:33am

Hi ShaneCCC,

https://devtalk.nvidia.com/default/topic/1068583/jetson-nano/jetpack-4-3-l4t-r32-3-1-released/post/5425706/#5425706

The jetson-io.py is not support the eMMC of Nano.

Thanks!

Karis · February 18, 2020, 1:13am

Hi ShaneCCC,

Any update?

Thanks!

ShaneCCC · February 18, 2020, 3:55am

Due to the jetson-io not support on the emmc nano version, could you check the pin address from the TRM and use devmem2 to read it to confirm the configure is correct. Also you can write to correct configure and try the SPI function.

ShaneCCC · February 18, 2020, 4:40am

@Karis
Still can try to modify the ./kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0000-xxx.dtsi
Change the rsvdx to spi

spi1_mosi_pc0 {
                                nvidia,pins = "spi1_mosi_pc0";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        spi1_miso_pc1 {
                                nvidia,pins = "spi1_miso_pc1";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        spi1_sck_pc2 {
                                nvidia,pins = "spi1_sck_pc2";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        spi1_cs0_pc3 {
                                nvidia,pins = "spi1_cs0_pc3";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        spi1_cs1_pc4 {
                                nvidia,pins = "spi1_cs1_pc4";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        spi2_mosi_pb4 {
                                nvidia,pins = "spi2_mosi_pb4";
                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        spi2_miso_pb5 {
                                nvidia,pins = "spi2_miso_pb5";
                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        spi2_sck_pb6 {
                                nvidia,pins = "spi2_sck_pb6";
                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        spi2_cs0_pb7 {
                                nvidia,pins = "spi2_cs0_pb7";
                                nvidia,function = "rsvd2";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        spi2_cs1_pdd0 {
                                nvidia,pins = "spi2_cs1_pdd0";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

Karis · February 18, 2020, 4:54am

Hi ShaneCCC,

Thank you

I will try it.

Karis · February 21, 2020, 7:19am

Hi ShaneCCC,

is Nano have pinmux config file?

is any way to configuration spi funtion, I don’t want setting spi function by devmem2 on Nano.

Thank you!

Karis

ShaneCCC · February 21, 2020, 7:29am

You can modify the dts file like below link. Also confirm it with devmem2.

https://devtalk.nvidia.com/default/topic/1051483/jetson-nano/spi-communication-on-jetson-nano/post/5354646/#5354646