acquirerrd usb3.0 port0 and usb3.0 port1 at the same time?

My custom board acquirerrd usb3.0 port0 and usb3.0 port1 at the same time.
I try to modity below, and re-compiler dtb

/kernel/arch/arm/boot/dts/tegra124-jetson_tk1-pm375-000-c00-00.dts
        xusb@70090000 {
                /* nvidia,uses_external_pmic;
                nvidia,gpio_controls_muxed_ss_lanes; */
                nvidia,gpio_ss1_sata = <0>;
                nvidia,portmap = <0x703>; /* SSP0, SSP1 USB2P0, USB2P1, USBP2 */
                nvidia,ss_portmap = <0x20>; /* SSP0 on USB2P0, SSP1 on USB2P2 */
                nvidia,lane_owner = <6>; /* USB3P0 USB3P1 */
                nvidia,ulpicap = <0>; /* No ulpi support. can we remove */
                status = "okay";
        };

I find code below

kernel/drivers/platform/tegra/tegra_usb_pad_ctrl.c //line352

val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);   
	/* USB3_SS port1 can either be mapped to SATA lane or PCIe lane1 */
	if (lane_owner & BIT(0)) {
		val &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0;
		val |= XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_OWNER_USB3_SS;
	} else if (lane_owner & BIT(1)) {  //BIT(1)=1=0x2
		val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE1;
		val |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE1_OWNER_USB3_SS;
	}

//To control usb3_lane1 with lane_owner,BIT(1)

	/* USB_SS port0 is alwasy mapped to PCIe lane0 */
	if (lane_owner & BIT(2)) {//BIT(2)=1=0x4
		val &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE0;
		val |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_PAD_LANE0_OWNER_USB3_SS;
	}
	writel(val, pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);

	/* Bring enabled lane out of IDDQ */
	val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
	if (lane_owner & BIT(0))
		val |= XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
	else if (lane_owner & BIT(1))
		val |= XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
	if (lane_owner & BIT(2))
		val |= XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
	writel(val, pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
udelay(1);

I have confirm lsusb
ubuntu@tegra-ubuntu:~$ lsusb -t
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=tegra-xhci/2p, 5000M
/: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=tegra-xhci/6p, 480M
|__ Port 3: Dev 2, If 0, Class=Hub, Driver=hub/4p, 480M
|__ Port 1: Dev 3, If 0, Class=Human Interface Device, Driver=usbhid, 1.5M
|__ Port 1: Dev 3, If 1, Class=Human Interface Device, Driver=usbhid, 1.5M
|__ Port 3: Dev 4, If 0, Class=Mass Storage, Driver=usb-storage, 480M
|__ Port 4: Dev 5, If 0, Class=Human Interface Device, Driver=usbhid, 1.5M

usb3_lane1 has still disable,usb3_lane0 enable

Is there maybe other idea that enable usb3.0 port0 and usb3.0 port1 at the same time?

Hi nuu9323226,

have you managed to use both USB_SS#0 and USB_SS#1 at the same time?
Is that working properly in the kernel?

I need to do the same on a custom board and I would like to know if that’s supported.

Hi dimtass,
Is it possible to simulate your case on tk1? Looks like you use the custom board.

Hi DaneLL,

well I’ve find a solution that worked for me. The default case is that SSP0 is on USB2P2 and I wanted to validate that SSP1 can work on the same USB2P2 port. So, I’ve done the following:

arch/arm/boot/dts/tegra124-hd271.dts

vidia,portmap = <0x703>; /* SSP0, SSP1, USB2P0, USBP1, USBP2 */
nvidia,ss_portmap = <0x27>; /* SSP1 on USB2P2 */
nvidia,lane_owner = <6>; /* USB3P0 USB3P1 */

In arch/arm/mach-tegra/board-ardbeg.c, commented out this line:

xusb_pdata.portmap &= ~(TEGRA_XUSB_SS_P1);

And edited the boot args in u-boot to the following:

usb_port_owner_info=3 lane_owner_info=6

Tested USB3.0 and it worked fine:

root@lalaland-tk1:/# lsusb -t
/:  Bus 02.Port 1: Dev 1, Class=root_hub, Driver=tegra-xhci/2p, 5000M
    |__ Port 2: Dev 2, If 0, Class=Hub, Driver=hub/7p, 5000M
        |__ Port 1: Dev 3, If 0, Class=Mass Storage, Driver=usb-storage, 5000M
        |__ Port 3: Dev 4, If 0, Class=Mass Storage, Driver=usb-storage, 5000M
        |__ Port 4: Dev 5, If 0, Class=Vendor Specific Class, Driver=lan78xx, 5000M
/:  Bus 01.Port 1: Dev 1, Class=root_hub, Driver=tegra-xhci/6p, 480M
    |__ Port 2: Dev 2, If 0, Class=Hub, Driver=hub/7p, 480M
    |__ Port 3: Dev 3, If 0, Class=Hub, Driver=hub/7p, 480M

Hi dimtass,
Good to hear you have the solution and many thanks for sharing to other users.

Did your LAN7800 works as well ? Our LAN7800 can only linked under USB2.0, not workable under USB3.0 speed.

Hi Chester, sorry but it’s being so long since this project and I really don’t remember any details regarding that.

Thanks for your reply.