A have recently design a board with tegra K1,the design is almost the same as the jetson K1 board.I successfully found the usb device of the tegra K1 in recoverying mode ,but failed flashing the emcc flash.However, when on jetson K1 the flashing is always sucessful.
It stopped at “sending file: tegra124-jetson_tk1-pm375-000-c00-00.dtb”.
I made the uart4 connected to the computer uart and I get the log"SDRAM initialization failed with 0x0 , sdram init failed with error 0x3 in DownloadFile func at 1118 line"
I don’t know what’s wrong with the sdram ,the sdrams selected are the same as the sdrams on jetson K1.
What I can get from the log? I check my hardware design schematic and is the same as the schematic of jetson k1.
Here’s a list of nvflash error codes which might help:
https://devtalk.nvidia.com/default/topic/831539/embedded-systems/now-unable-to-flash-jetson-tk1/post/4528073/#4528073
The 0x3 shows as:
"method or interface is not initialized"
“Why” it isn’t initialized is beyond my knowledge.
I put a nvtest tool for emmc and sdram on the below link:
https://drive.google.com/file/d/0B9JDdk5z6XBENXMydzJWTWYzSnc/view?usp=sharing
The nvtest is run from host pc under windows OS.
emmc.bat will test emmc
runmats.bat and runreg.bat will test sdram
each test could finish within 5 min, run each test batch file after you reset the DUT to recovery mode.
Refer to the log(ddr_792_pass.log and emmc_pass.log),total failures: 0 means the interface read&write is pass.
The failure means a hardware issue may related to soldering or chip damage or bad signal timing…
The defalt sdram config file point to Hynix_2GB_H5TC4G63AFR-RDA_792MHz.cfg. you can switch to Hynix_2GB_H5TC4G63AFR-RDA_300MHz.cfg which will give more margin to find if the sdram timing need fine tune on your board.
Thanks a lot. I have found my error.
A simple net name error,just because the two nets have the similar name .
Thank you . I have already found my mistake.
Hello, Asong
I have encountered the same problem with you! I am stuck at “sending file: tegra124-jetson_tk1-pm375-000-c00-00.dtb” and the serial port shown “SDRAM initialization failed with 0x0 , sdram init failed with error 0x3 in DownloadFile func at 1118 line”
I use a VMware host with ubuntu 14 in Win10 os.
You said you have solved the problem. Could you give me any detail about how you got it ?
Great thanks!
From Asong’s update “A simple net name error,just because the two nets have the similar name”
Seems this is a hardware issue, two signals were short on his PCB.
Would you please run nvtest on your board ?
Hi All,
We designed a custom board with Tegra K1 and used H5TC4G63AFR-RDA DDR (same as of Jetson board). We are facing issues when running the DDR at 924MHz.
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When we used the existing Jeston BCT/CFG file PM375_Hynix_2GB_H5TC4G63AFR_RDA_924MHz.cfg (that is present in L4T package R21.4) in our custom board, during booting we faced Linux kernel crashing/unstable.
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Then we tried to generate the cfg using Tegra_K1_Memory_CharacterizationV1.0.1 tool, but it failed in Sanity [runme_instead_TK1_Sanity.bat] at 924MHz. And for 792 MHz sanity test passed 1 out of 3 times. And lower frequency it always passed. We tried changing the “TK1_DDR_Board_delay” excel file according to our PCB, but still it doesn’t help, we are facing the same issues.
We did DDR test using the memtester in L4T Ubuntu, memtester fails for 924MHz and 792MHz.
We searched in the forum and internet and got this “nvtest_tk1.7z” from “https://devtalk.nvidia.com/default/topic/841202/a-tegra-k1-problem-on-sdrams-found-when-flashing-the-emcc-flash-probably-something-on-hardware/?offset=3”. We used this “Hynix_2GB_H5TC4G63AFR-RDA_792MHz.cfg” and kernel is stable and memtester passes.
How do we generate the correct cfg file for 924Mhz? Are we missing anything, since we are using the same chip as jetson and have also accounted for the different trace lengths in our PCB
We need similar cfg for 924MHz.
Thanks in advance.
Hi Jeslin,
We are also facing the same exact issue. Are you able to resolve it? If so, please help with the steps you did to get 924MHz working for your board.
Hello,
I’ve been directed to this thread to understand how to create a memory parameter file.
I’m wondering how I can obtain my DDR3L memory par file?
I found in the directory Tegra_K1_Memory_CharacterizationV1.0.1\extras\param_files the memory I’m using is different but similar to Micron_2GB_MT41K256M16HA_ddr3.par.
Not all of the values are clearly taken from the datasheet so I need to understand where these values come from. And how I can make the .par file from scratch.