Using csi2 with tc358840 using device tree on r24.1

We are using a tc358840 hdmi to csi chip and connecting it to csia and csib on the TX1. We’re trying to move to r24.1 to hopefully improve the stream rate for 4k@30. Are there any examples of how to connect cisco’s tc358840 driver to the system using the device tree? I’ve been poring over the code, but it’s very confusing. There are references to csi-port, bus-width, clock-lanes, and data-lanes that don’t seem to be consistently used in the code. We’ve connected a similar driver in r23.2 using the platform driver, but it looks like r24.1 expects to use the media controller and the device tree.

Any suggestions or examples?

Correction to above post:

We’re using csia and csib for one set of 4 lanes and csic and csid for the next set of 4 lanes. The tc358840 needs 8 lanes for 4k@30 video.

Hi

We have developed a driver for the TC358840 and are sharing it on Github. You can check it out here: https://github.com/InES-HPMM/linux-l4t/wiki/hdmi2csi

We have also connected the TC358840 to CSIA and CSIB. But be aware that we are using a custom host driver (tegra_vi2). Our example of a device tree file is here: linux-l4t/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts at hdmi2csi/l4t-r23-1 · InES-HPMM/linux-l4t · GitHub
But again this depends on the tegra_vi2 and tc358840 driver that you use.

Regards
Tobias

Edit: For R24.1 the device tree file is here: linux-l4t/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts at hdmi2csi/l4t-r24-1-dev-4K · InES-HPMM/linux-l4t · GitHub

This has been very helpful. Thank you.

Hi,

Auvidea is developing a carrier board for the TX1, which has 2 of the Toshiba TC358840 devices integrated. One connects with 8 lanes (so 2 4-lane CSI-2 interfaces) and one with just one 4-lane CSI-2 interface. The TX1 only has 12 lanes in total. The first chip should be able to do 2160p30 (4k with 30p)- the second 1080p60.

The PCBs of the J130 just arrived. They are scheduled to be stuffed next week. If things go right we should be able to send out first boards to beta customers in 2 weeks. Please let me know, if you are interested. More information can be found on diydrones:
[url]NVIDIA's TX1 SoC now comes on a credit-card sized module - Blogs - diydrones.

Key features of the J130:

• 2x CAN
• 1x GbE (Gigabit Ethernet)
• USB 3 hub (Cypress chip) for 5 USB3 ports in total
• high USB 3 power (on board 5V 10A power supply)
• PCIe slot with 4 lanes
• SATA connector
• HDMI input with 2160p30 (4k) with 8 CSI-2 lanes - TC358840
• HDMI input with 1080p60 with 4 CSI-2 lanes - TC358840
• size: 74 x 110 mm
• first prototypes August 2016

Hi All,

I need to connect 4 image sensors to VI ports through MIPI CSI. Control interface of all sensors is I2C.

1. Is it mandatory that all four should be added in I2c controller of VI block (i.e vi-i2c) ??
2. I am referring “tegra210-camera-e3326-a00.dtsi”. But I could not find CSI properties like clock-lanes, data-lanes, etc.

Can someone clarify above queries?

Thanks
Palani

1. The sensors can be able to access in any available i2c bus.
2. The following nodes indicate the csi pad configuration.

mode0 { // OV5693_MODE_2592X1944
mclk_khz = “24000”;
num_lanes = “2”;
tegra_sinterface = “serial_c”;
discontinuous_clk = “no”;