I am trying to capture via I2S on the X1 on my custom hardware. Currently I have an external ADC which is suppossed to send I2S data to the I2S0 port of the X1 SOM.
Unfortunately I am using my externel ADC in a master mode with the X1 as a Slave and I am using the AUDIO_MCLK source as my system clock source for my ADC.
Checking the AUDIO_MCLK pin on a scope shows now output though.
To clarify I am using pin F1. I also checked this pin on the Jetson X1 eval board where it is routed to the J21 expansion header (NVIDIA Jetson TX1 J21 Header Pinout - JetsonHacks) and it too shows no output.
I also tried enabling via /sys/kernel/debug/clock/ by setting the states to ‘1’ but still getting no output.
I have the following pinmux settings for the clk in the file
Being that this aud_mclk is muxed with gpio 216, i tested setting it to GPIO and was able to see the switch on the J21 header so I know it is being set properly.
From HW perspective, the connection of AUD_MCLK is OK.
I’m not familiar with SW configuration, but maybe you can check section 12.6.107 APBDEV_PMC_CLK_OUT_CNTRL_0 of TX1 TRM doc, seems the dap_mclk1_out is the corresponding control bits. Hope this can help you.
Again i’ve checked on my hardware as well as the jetson board and both show the same symptom where the audio_mclk0 is not producing any signal. I’ve tried probing it will also running aplay and arecord to see if that was the issue but still no clock is generated
I’m just trying to make that clock produce the standard 24MHz i need.
Does anyone know how in software to get this pin ‘F1’ AUDIO_MCLK to produce this output.
As I know, Jetson TX1 does not mount audio codec. You may check the driver sound/soc/tegra/tegra_rt5639.c and go through mclk-related function. A codec driver should be up first.
i put my pinmux setting up above. i believe i only have to set it in the dts file like shown. can you verify?
I don’t believe that it is being exported as a GPIO. is there any way to verify this? I previously did export it as a test just to see if i had it as a correct pin and upon exporting (using /sys/class/gpio) i was able to toggle it and see it on the scope.
I am currently mounting the audio codec tegra_t210ref_mobile_rt565x_alt.c found in sound/soc/tegra-alt/ and am force mounting it as a dummy codec (since i am using an external codec).
I also manually made sure all the clocks requested in that driver get set. Unfortunately i dont konw if any of these clocks apply to AUD_MCLK though. Seems they refer to mclk as ‘pll_a’.
I previously had it as DISABLE and switched it to test some. It is back to ENABLE.
What is the difference between the tegra-alt and regular tegra folders in the sound driver’s folder. I see both contain a variation of an rt5639 driver but the tegra-alt is what is used by default.
What clock in the clock tree actually is the AUD_MCLK line? There isn’t a clock that is the exact name and there are many. Again i previously set all the clocks in the the clock tree to state on but still did not get a clock. Here are some i believe would be relevant.
pll_a on 1 x9.5.. 368639844
pll_a_out0 on 3 10.0 36863985
extern1 on 3 3.0 12287995
clk_out_1 on 2 1.0 12287995
d_audio $ on 2 1.0 36863985
vdd_core 800 mV
d_audio_slcg_ovr $ off 0 36863985
dmic3 off 0 11.0 3351272
dmic2 off 0 11.0 3351272
dmic1 off 0 11.0 3351272
spdif_out $ off 0 21.0 1755428
vdd_core 0 mV
i2s4 off 0 5.50 6702543
i2s3 off 0 5.50 6702543
i2s1 off 0 5.50 6702543
i2s0 on 1 24.0 1536000
*pll_a_out0_out_adsp off 0 1.0 36863985
*pll_a_out_adsp off 0 1.0 368639844
i2s4_sync on 1 24000000
i2s3_sync on 1 24000000
*audio3 off 0 24000000
i2s2_sync on 1 24000000
i2s1_sync on 1 24000000
*audio1 off 0 24000000
i2s0_sync on 1 24000000
spdif_in_sync on 1 24000000
*audio2_dmic off 0 24000000
*audio1_dmic off 0 24000000
*audio0_dmic off 0 24000000
*audio off 0 24000000
*audio_2x off 0 x2 48000000
*audio4 off 0 24000000
*audio2 off 0 24000000
*audio0 off 0 24000000
And yes even though i set all the pinmux values correctly (to my knowledge) in the pinmux dts, the gpio driver at some level must still be stealing that pin.
I had the same situation for the other I2S pins I used as well (I2S1_SDATA_IN, I2S1_LRCK, I2S1_SCLK). For each of these i had to run export then unexport on their GPIO pins to get them to work.
Hello, x1tester62:
That’s weird. Would you please do GPIO export/unexport as a WAR and keep your development going. I will try to check this issue in my platform. It may take some time.
I think having an actual bit clock is better, but you could rig something based on data level changes (any differential signal, such as this, has lower jitter with a real clock…if having one less wire is more important you can estimate a clock based on data…it depends on how you feel about jitter). The other clock would also be known as the word clock or left-right clock, but this may be referred to in some of the docs as the audio sync clock…I can’t guarantee it but pin 12 (abbreviated AUDIO_I2S_SRCLK_3V3) is probably the clock for selecting left-right. Maybe someone could verify this.
I am trying to import sound via I2S to an adafruit microphone(3421).
Can anybody help by confirming the pins(audio_mclk and sclk) and help with further steps.
Any help would be highly appreciated.